kosher arch creation #28
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rhelmot
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Nov 4, 2020
* Working on AVR lifter * Implemented basic BPF support for angr. * BPF: NEG is not invert :-( * Move instruction endness to the new thing * Specify instruction_endness for ArchBPF. * Add a name attribute to each BPF Instruction class. * Move DATA_BASE and TEMP_BASE to ArchBPF. * Remove redundant code from lift_bpf. * Implement ret as returning to the max_inst_id. * Fix a bug in NEG. * small fixes. * Add two test cases for the BPF backend. * Add angr lifecycle picture and fix typos * Update readme * Bugfixes to BF lifter * Add per-architecture registration * Add `is_default` flags to angr-platforms lifters (#16) * Fix BPF loader overriding ELF loader for MSP430 * Add the is_default flag to the bf loader * fix(arch_bf): `register_names[8]` should be "ptr", not "pc" This bug caused the lifter to incorrectly believe that `pc` and `ptr` are the same register (since `lookup_register` does a int -> name -> int roundtrip) so the VEX was wrong (the ptr modifications were missing). * fix(lift_bf): adapt to new `__init__` signature of gymrat lifter `__init__` now only takes two arguments, the remaining ones need to be passed using the `_lift` method. * fix(avr): add `__init__.py` to allow module import from avr package * avr: fix PC handling + some typos in existing instructions * fix(avr): move data memory to higher address This allows more program memory. It's now exactly 50/50 for program and data memory. * fix(arch_avr): add all registers to register_names * fix(arch_avr): add lowercase alias for SP register * fix(arch_avr): add more metadata (sp_offset, call_pushes_ret) * feat(avr): implement missing flag calculation, fix some errors * fix(lift_avr): adapt test code to gymrat changes * feat(lift_avr): implement more instructions * fix(feat_avr): verify that LDDY opcode is correct, remove TODO I checked with avr-gcc which does produce this opcode for this instruction, so I assume it is correct. * docs(feat_avr): cleanup comments * fix(lift_avr): self.bitsize -> self.bitwidth * avr: group instructions by category This makes it easier to refactor things that only affect a specific group of instructions. For example, if we want to change how the PC is handled, most of the instructions that need to be changed are the in the control-flow group so having them close together makes this easier. * feat(avr): handle RAMPD for lds/sts * fix(avr): do not write to register in CPI instruction * fix(avr): unify store instructions + handle address modify correctly When the address is updated, we also need to update the segment register as stated in the ISA. * fix(avr): correct semantics for LAC/LAT/LAS instructions * refactor(avr): unify LD* instructions, handle RAMP registers * refactor(avr): ld/st: move address handling into common superclass * refactor(avr): map data at low address, program at high address This has the advantage that data address can be used without translating. Data addresses are used directly much more often than program addresses, so they are harder to translate everywhere. For example, with this approach, the following will now work: ``` state.mem[state.regs.sp + 1].byte.array(4).concrete ``` Previsouly, that would give incorrect results because you needed to add the data offset. * fix(avr): don't accept wrong encodings for stX/ldX (fixes pop) This bug made pop decode as a `ld X+q`. * fix(avr): opcode for LAC instruction was wrong * fix(avr): make put_reg_pair work correctly * avr: change SP in register file to point to bottom of stack * avr: some more fixes * Add cybertronix64k * Update for plugin api refactor * pyvex.lift -> pyvex.lifting * SimEngineBF: fix engine registration * Add engine preset for SimEngineCT64K * Prevent default project configuration from being run in ct64 to prevent creation of externs object * Update for files refactor * Split ct64 test into fast/slow * upgrade CI to xenial * Migrate to Python 3 (#21) * The only thing more nonsensical than large brainfuck programs is doing trivial tasks in python 3 (implement py3k support) * *gently pushes my mop through the room* * *snaps fingers* * *snaps fingers angrily* * Strip custom_ prefix from CLE arguments which aren't really all that custom * You know, if we use synthetic fabrics to build our code out of, a lot les LINT comes out in the wash.... grumble... * Fine, no wildcards i guess * remove a few IS_SYSCALL descriptors - don't need these anymore * Fix terrible bugs * Stop BIT instruction from storing its result * Fix JL implementation * Fix overflow flag for MSP430 SUB(C) instruction * Fix MSP430 carry bit logic (#26) * Fix MSP430 SUB instruction carry bit logic * Reimplement ADDC, SUB, SUBC as ADD subclasses * Separate implementation for MSP430 SUB and ADD * Fix MSP430 SUBC carry for byte mode * Update arch_bf to use the latest Arch infrastructure. * SimEngineBF: Implement lift(). * less restrictive (more correct) test assertions * kosher arch creation (#28) * make bf tests ACTUALLY DO WHAT THEY SAY THEY DO. they don't work anymore as a result. * Fix everything except the bf lifter * ok so that was a bad idea * nuke travis * Fix ct64 engine for eleventh hour refactor * bf lifter has been broken but only now is being tested. mark as broken * Fix lifter BF (#29) * Install sub-modules with pip by using find_packages. Sub-modules (e.g. msp430) are not found when angr-platforms is installed with pip, because only the top-level module is listed. Using setuptools' find_packages function corrects this. Fixes #30. * Adapt to CLE api changes * Additionally fix apis * risc-v 32 bit lifter (#35) * Add more information and capstone disasm support to ArchRISCV (#36) * fix main for BF lifter the used API has changed in the latest version of angr. Essentially the arguments passed to the lifter changed and 'lift' has been replaced with '_lift' * fix outdated code in tutorial/2_arch.md the code presented to create the Arch does not work anymore biggest issue is that bits has to be defined before calling super on 'Arch'. I've also made use of the new 'registers_list' the same way it is used in the bf code * add the sparc arch * sparc's test file * add the sparc 32 bit architect * memory.load() expects explicit sizes now. * Use the ListPages page model for ct64. * Implemented syscalls in RISCV * Add azure CI * try to make it work * Add syscall number to new state * lint Co-authored-by: Eric Gustafson <edg@cs.ucsb.edu> Co-authored-by: Fish <fish@cs.ucsb.edu> Co-authored-by: lockshaw <mastakata3@yahoo.com> Co-authored-by: Benno Fünfstück <benno.fuenfstueck@gmail.com> Co-authored-by: Audrey Dutcher <audrey@rhelmot.io> Co-authored-by: Maksim Malyutin <m.malyutin@embedi.com> Co-authored-by: Fish <ltfish@users.noreply.github.com> Co-authored-by: Hidde-Jan Jongsma <me@hidde-jan.nl> Co-authored-by: Whatang <mike@whatang.org> Co-authored-by: stefanberg96 <stefanberg96@users.noreply.github.com> Co-authored-by: wwwzbwcom <zbwhome@outlook.com> Co-authored-by: Jakob Koschel <jakobkoschel@aim.com> Co-authored-by: zd99921 <61439820+zd99921@users.noreply.github.com> Co-authored-by: Mika <mika.brattain@centauricorp.com> Co-authored-by: Kevin Phoenix <kevin@kphoenix.us> Co-authored-by: Moritz Eckert <mo@mightym0.de>
ltfish
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Apr 15, 2021
* Working on AVR lifter * AVR improvements (WIP) | fix minor issues in #17 (#42) * Working on AVR lifter * Implemented basic BPF support for angr. * BPF: NEG is not invert :-( * Move instruction endness to the new thing * Specify instruction_endness for ArchBPF. * Add a name attribute to each BPF Instruction class. * Move DATA_BASE and TEMP_BASE to ArchBPF. * Remove redundant code from lift_bpf. * Implement ret as returning to the max_inst_id. * Fix a bug in NEG. * small fixes. * Add two test cases for the BPF backend. * Add angr lifecycle picture and fix typos * Update readme * Bugfixes to BF lifter * Add per-architecture registration * Add `is_default` flags to angr-platforms lifters (#16) * Fix BPF loader overriding ELF loader for MSP430 * Add the is_default flag to the bf loader * fix(arch_bf): `register_names[8]` should be "ptr", not "pc" This bug caused the lifter to incorrectly believe that `pc` and `ptr` are the same register (since `lookup_register` does a int -> name -> int roundtrip) so the VEX was wrong (the ptr modifications were missing). * fix(lift_bf): adapt to new `__init__` signature of gymrat lifter `__init__` now only takes two arguments, the remaining ones need to be passed using the `_lift` method. * fix(avr): add `__init__.py` to allow module import from avr package * avr: fix PC handling + some typos in existing instructions * fix(avr): move data memory to higher address This allows more program memory. It's now exactly 50/50 for program and data memory. * fix(arch_avr): add all registers to register_names * fix(arch_avr): add lowercase alias for SP register * fix(arch_avr): add more metadata (sp_offset, call_pushes_ret) * feat(avr): implement missing flag calculation, fix some errors * fix(lift_avr): adapt test code to gymrat changes * feat(lift_avr): implement more instructions * fix(feat_avr): verify that LDDY opcode is correct, remove TODO I checked with avr-gcc which does produce this opcode for this instruction, so I assume it is correct. * docs(feat_avr): cleanup comments * fix(lift_avr): self.bitsize -> self.bitwidth * avr: group instructions by category This makes it easier to refactor things that only affect a specific group of instructions. For example, if we want to change how the PC is handled, most of the instructions that need to be changed are the in the control-flow group so having them close together makes this easier. * feat(avr): handle RAMPD for lds/sts * fix(avr): do not write to register in CPI instruction * fix(avr): unify store instructions + handle address modify correctly When the address is updated, we also need to update the segment register as stated in the ISA. * fix(avr): correct semantics for LAC/LAT/LAS instructions * refactor(avr): unify LD* instructions, handle RAMP registers * refactor(avr): ld/st: move address handling into common superclass * refactor(avr): map data at low address, program at high address This has the advantage that data address can be used without translating. Data addresses are used directly much more often than program addresses, so they are harder to translate everywhere. For example, with this approach, the following will now work: ``` state.mem[state.regs.sp + 1].byte.array(4).concrete ``` Previsouly, that would give incorrect results because you needed to add the data offset. * fix(avr): don't accept wrong encodings for stX/ldX (fixes pop) This bug made pop decode as a `ld X+q`. * fix(avr): opcode for LAC instruction was wrong * fix(avr): make put_reg_pair work correctly * avr: change SP in register file to point to bottom of stack * avr: some more fixes * Add cybertronix64k * Update for plugin api refactor * pyvex.lift -> pyvex.lifting * SimEngineBF: fix engine registration * Add engine preset for SimEngineCT64K * Prevent default project configuration from being run in ct64 to prevent creation of externs object * Update for files refactor * Split ct64 test into fast/slow * upgrade CI to xenial * Migrate to Python 3 (#21) * The only thing more nonsensical than large brainfuck programs is doing trivial tasks in python 3 (implement py3k support) * *gently pushes my mop through the room* * *snaps fingers* * *snaps fingers angrily* * Strip custom_ prefix from CLE arguments which aren't really all that custom * You know, if we use synthetic fabrics to build our code out of, a lot les LINT comes out in the wash.... grumble... * Fine, no wildcards i guess * remove a few IS_SYSCALL descriptors - don't need these anymore * Fix terrible bugs * Stop BIT instruction from storing its result * Fix JL implementation * Fix overflow flag for MSP430 SUB(C) instruction * Fix MSP430 carry bit logic (#26) * Fix MSP430 SUB instruction carry bit logic * Reimplement ADDC, SUB, SUBC as ADD subclasses * Separate implementation for MSP430 SUB and ADD * Fix MSP430 SUBC carry for byte mode * Update arch_bf to use the latest Arch infrastructure. * SimEngineBF: Implement lift(). * less restrictive (more correct) test assertions * kosher arch creation (#28) * make bf tests ACTUALLY DO WHAT THEY SAY THEY DO. they don't work anymore as a result. * Fix everything except the bf lifter * ok so that was a bad idea * nuke travis * Fix ct64 engine for eleventh hour refactor * bf lifter has been broken but only now is being tested. mark as broken * Fix lifter BF (#29) * Install sub-modules with pip by using find_packages. Sub-modules (e.g. msp430) are not found when angr-platforms is installed with pip, because only the top-level module is listed. Using setuptools' find_packages function corrects this. Fixes #30. * Adapt to CLE api changes * Additionally fix apis * risc-v 32 bit lifter (#35) * Add more information and capstone disasm support to ArchRISCV (#36) * fix main for BF lifter the used API has changed in the latest version of angr. Essentially the arguments passed to the lifter changed and 'lift' has been replaced with '_lift' * fix outdated code in tutorial/2_arch.md the code presented to create the Arch does not work anymore biggest issue is that bits has to be defined before calling super on 'Arch'. I've also made use of the new 'registers_list' the same way it is used in the bf code * add the sparc arch * sparc's test file * add the sparc 32 bit architect * memory.load() expects explicit sizes now. * Use the ListPages page model for ct64. * Implemented syscalls in RISCV * Add azure CI * try to make it work * Add syscall number to new state * lint Co-authored-by: Eric Gustafson <edg@cs.ucsb.edu> Co-authored-by: Han Dai <github@daihan.me>
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required by angr/archinfo#69