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Modelling and simulation of a polynomial evaluator in VHDL using stepwise refinement.

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Evaluating a simple polynomial function in VHDL

This repository provides a concise, easy-to-follow, method of modelling and simulation of a polynomial function in VHDL using stepwise refinement. Block diagram of operation

Software

The codes were developed using industry standard software, Intel Quartus Prime (digital system design) and ModelSim (simulation software).

Usage

The codes were developed in this particular order:

  1. case_syd - high-level code for polynomial evaluation.
  2. vec_syd - low-level code for polynonial evaluation.
  3. validOUT - low-level code with controlled output.
  4. genericD - adapted generic code.

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Modelling and simulation of a polynomial evaluator in VHDL using stepwise refinement.

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