WIP: testing new master+wip yosys

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
antmicro · Jun 18, 2020 · 8fab833 · 8fab833
1 parent a2ab741
commit 8fab833
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Showing 4 changed files with 6 additions and 6 deletions.
diff --git a/xc/common/primitives/slicem/dram_2_output_stub.sim.v b/xc/common/primitives/slicem/dram_2_output_stub.sim.v
@@ -1,6 +1,6 @@
 // To ensure that all DRAMs are co-located within a SLICE, this block is
 // a simple passthrough black box to allow a pack pattern for dual port DRAMs.
-(* whitebox *)
+(* lib_whitebox *)
 module DRAM_2_OUTPUT_STUB(
     input SPO, DPO,
     output SPO_OUT, DPO_OUT

diff --git a/xc/common/primitives/slicem/dram_4_output_stub.sim.v b/xc/common/primitives/slicem/dram_4_output_stub.sim.v
@@ -1,6 +1,6 @@
 // To ensure that all DRAMs are co-located within a SLICE, this block is
 // a simple passthrough black box to allow a pack pattern for dual port DRAMs.
-(* whitebox *)
+(* lib_whitebox *)
 module DRAM_4_OUTPUT_STUB(
     input DOA, DOB, DOC, DOD,
     output DOA_OUT, DOB_OUT, DOC_OUT, DOD_OUT

diff --git a/xc/common/primitives/slicem/dram_8_output_stub.sim.v b/xc/common/primitives/slicem/dram_8_output_stub.sim.v
@@ -1,6 +1,6 @@
 // To ensure that all DRAMs are co-located within a SLICE, this block is
 // a simple passthrough black box to allow a pack pattern for dual port DRAMs.
-(* whitebox *)
+(* lib_whitebox *)
 module DRAM_8_OUTPUT_STUB(
     input DOA1, DOB1, DOC1, DOD1, DOA0, DOB0, DOC0, DOD0,
     output DOA1_OUT, DOB1_OUT, DOC1_OUT, DOD1_OUT, DOA0_OUT, DOB0_OUT, DOC0_OUT, DOD0_OUT

diff --git a/xc/xc7/yosys/synth.tcl b/xc/xc7/yosys/synth.tcl
@@ -11,10 +11,10 @@ yosys -import
 #
 # Do not infer IOBs for targets that use a ROI.
 if { $::env(USE_ROI) == "TRUE" } {
-    synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp
+    synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp -noiopad -nowidelut
 } else {
     # Read Yosys baseline library first.
-    read_verilog -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v
+    read_verilog -lib -specify -D_EXPLICIT_CARRY +/xilinx/cells_sim.v
     read_verilog -lib +/xilinx/cells_xtra.v
 
     # Overwrite some models (e.g. IBUF with more parameters)
@@ -23,7 +23,7 @@ if { $::env(USE_ROI) == "TRUE" } {
     hierarchy -check -auto-top
 
     # Start flow after library reading
-    synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp -iopad -run prepare:check
+    synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp -nowidelut -run prepare:check
 }
 if { [info exists ::env(INPUT_XDC_FILE)] && $::env(INPUT_XDC_FILE) != "" } {
   read_xdc -part_json $::env(PART_JSON) $::env(INPUT_XDC_FILE)