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Documenting the Xilinx 7-series bit-stream format.
Renode - virtual development tool for multinode embedded networks
SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
Small footprint and configurable DRAM core
A FPGA friendly 32 bit RISC-V CPU implementation
Build your hardware, easily!
Using VexRiscv without installing Scala
Primary GIT Repository for the Zephyr Project
An environment for building LiteX based FPGA designs. Makes it easy to get everything you need!
An open source replacement of the Xilinx bootgen application.
Repository for the RISC-V Getting Started Guide
SymbiFlow Website Source
Conda build recipes for the toolchains needed by LiteX / MiSoC firmware
Yosys Open SYnthesis Suite
This repository contains a sample code integrating
Docker image suitable for development, similar to what we have in CI
Docker image description with the newest Renode version