[SOL] Change encoding of callx instruction

llvm/lib/Target/SBF/Disassembler/SBFDisassembler.cpp

@@ -205,6 +205,12 @@ DecodeStatus SBFDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
     Op.setImm(Make_64(Hi, Op.getImm()));
     break;
   }
+  case SBF::JALX: {
+    if (STI.getFeatureBits()[SBF::FeatureCallxRegSrc]) {
+      Result = decodeInstruction(DecoderTableSBFv264, Instr, Insn, Address,
+                                 this, STI);
+    }
+  }
   }
 
   return Result;

llvm/lib/Target/SBF/SBF.td

@@ -13,51 +13,6 @@ include "SBFCallingConv.td"
 include "SBFInstrInfo.td"
 
 def SBFInstrInfo : InstrInfo;
-
-def DummyFeature : SubtargetFeature<"dummy", "isDummyMode",
-                                    "true", "unused feature">;
-
-def ALU32 : SubtargetFeature<"alu32", "HasAlu32", "true",
-                             "Enable ALU32 instructions">;
-
-def DwarfRIS: SubtargetFeature<"dwarfris", "UseDwarfRIS", "true",
-                               "Disable MCAsmInfo DwarfUsesRelocationsAcrossSections">;
-
-def FeatureSolana : SubtargetFeature<"solana", "IsSolana", "true",
-                                     "Enable Solana extensions">;
-
-def FeatureDynamicFrames : SubtargetFeature<"dynamic-frames", "HasDynamicFrames", "true",
-                                            "Enable dynamic frames">;
-
-def FeatureSdiv : SubtargetFeature<"sdiv", "HasSdiv", "true",
-                                   "Enable native SBF_SDIV support">;
-
-def FeatureRelocAbs64 : SubtargetFeature<"reloc-abs64", "UseRelocAbs64", "true",
-                                   "Fix 64bit data relocations">;
-
-def FeatureStaticSyscalls : SubtargetFeature<"static-syscalls", "HasStaticSyscalls", "true",
-                                   "Marker feature used for conditional compilation">;
-
-def FeatureDisableNeg : SubtargetFeature<"no-neg", "DisableNeg", "true",
-                                    "Disable the neg instruction">;
-
-def FeatureReverseSubImm : SubtargetFeature<"reverse-sub", "ReverseSubImm", "true",
-                                    "Reverse the operands in the 'sub reg, imm' instruction">;
-
-def FeatureDisableLddw : SubtargetFeature<"no-lddw", "NoLddw", "true",
-                                    "Disable the lddw instruction">;
-
-class Proc<string Name, list<SubtargetFeature> Features>
- : Processor<Name, NoItineraries, Features>;
-
-def : Proc<"generic", []>;
-def : Proc<"v1", []>;
-def : Proc<"v2", []>;
-def : Proc<"v3", []>;
-def : Proc<"probe", []>;
-def : Proc<"sbfv2", [FeatureSolana, FeatureDynamicFrames, FeatureSdiv, FeatureRelocAbs64, FeatureStaticSyscalls,
-                        FeatureDisableNeg, FeatureReverseSubImm, FeatureDisableLddw]>;
-
 //===----------------------------------------------------------------------===//
 // Assembly printer
 //===----------------------------------------------------------------------===//

llvm/lib/Target/SBF/SBFInstrInfo.td

@@ -11,6 +11,7 @@
 //===----------------------------------------------------------------------===//
 
 include "SBFInstrFormats.td"
+include "SBFTargetFeatures.td"
 
 // Instruction Operands and Patterns
 
@@ -56,13 +57,12 @@ def SBFNoALU32 : Predicate<"!Subtarget->getHasAlu32()">;
 def SBFSubtargetSolana : Predicate<"Subtarget->isSolana()">;
 def SBFHasLddw : Predicate<"!Subtarget->getNoLddw()">;
 def SBFNoLddw : Predicate<"Subtarget->getNoLddw()">;
-
-def SBFv2 : Predicate<"Subtarget->isSBFv2()">;
-def NoSBFv2 : Predicate<"!Subtarget->isSBFv2()">;
 def SBFHasNeg : Predicate<"!Subtarget->getDisableNeg()">;
 def SBFNoNeg: Predicate<"Subtarget->getDisableNeg()">;
 def SBFRevSub : Predicate<"Subtarget->getReverseSubImm()">;
 def SBFNoRevSub : Predicate<"!Subtarget->getReverseSubImm()">;
+def SBFCallxSrc : Predicate<"Subtarget->getCallXRegSrc()">, AssemblerPredicate<(all_of FeatureCallxRegSrc)>;
+def NoSBFCallxSrc : Predicate<"!Subtarget->getCallXRegSrc()">;
 
 def brtarget : Operand<OtherVT> {
   let PrintMethod = "printBrTargetOperand";
@@ -574,6 +574,18 @@ class CALLX<string OpcodeStr>
   let SBFClass = SBF_JMP;
 }
 
+class CALLX_SRC_REG<string OpcodeStr>
+    : TYPE_ALU_JMP<SBF_CALL.Value, SBF_X.Value,
+                   (outs),
+                   (ins GPR:$BrDst),
+                   !strconcat(OpcodeStr, " $BrDst"),
+                   []> {
+  bits<4> BrDst;
+
+  let Inst{55-52} = BrDst;
+  let SBFClass = SBF_JMP;
+}
+
 // Jump always
 let isBranch = 1, isTerminator = 1, hasDelaySlot=0, isBarrier = 1 in {
   def JMP : BRANCH<SBF_JA, "ja", [(br bb:$BrDst)]>;
@@ -583,8 +595,11 @@ let isBranch = 1, isTerminator = 1, hasDelaySlot=0, isBarrier = 1 in {
 let isCall=1, hasDelaySlot=0, Uses = [R11],
     // Potentially clobbered registers
     Defs = [R0, R1, R2, R3, R4, R5] in {
-  def JAL  : CALL<"call">;
-  def JALX  : CALLX<"callx">;
+  def JAL     : CALL<"call">;
+  def JALX    : CALLX<"callx">, Requires<[NoSBFCallxSrc]>;
+  let DecoderNamespace = "SBFv2" in {
+    def JALX_v2 : CALLX_SRC_REG<"callx">, Requires<[SBFCallxSrc]>;
+  }
 }
 
 class NOP_I<string OpcodeStr>
@@ -678,7 +693,8 @@ def : Pat<(i64 (and (i64 GPR:$src), 0xffffFFFF)),
 def : Pat<(SBFcall tglobaladdr:$dst), (JAL tglobaladdr:$dst)>;
 def : Pat<(SBFcall texternalsym:$dst), (JAL texternalsym:$dst)>;
 def : Pat<(SBFcall imm:$dst), (JAL imm:$dst)>;
-def : Pat<(SBFcall GPR:$dst), (JALX GPR:$dst)>;
+def : Pat<(SBFcall GPR:$dst), (JALX GPR:$dst)>, Requires<[NoSBFCallxSrc]>;
+def : Pat<(SBFcall GPR:$dst), (JALX_v2 GPR:$dst)>, Requires<[SBFCallxSrc]>;
 
 // Loads
 let Predicates = [SBFNoALU32] in {

llvm/lib/Target/SBF/SBFSubtarget.cpp

@@ -39,10 +39,15 @@ void SBFSubtarget::initializeEnvironment(const Triple &TT) {
   HasJmpExt = false;
   HasJmp32 = false;
   HasAlu32 = false;
-  HasDynamicFrames = false;
   HasSdiv = false;
   UseDwarfRIS = false;
-  IsSBFv2 = false;
+
+  // SBFv2 features
+  HasDynamicFrames = false;
+  DisableNeg = false;
+  ReverseSubImm = false;
+  NoLddw = false;
+  CallxRegSrc = false;
 }
 
 void SBFSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
@@ -66,7 +71,6 @@ void SBFSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
   }
 
   if (CPU == "sbfv2") {
-    IsSBFv2 = true;
     if (!HasDynamicFrames)
       report_fatal_error("sbfv2 requires dynamic-frames\n", false);
   }

llvm/lib/Target/SBF/SBFSubtarget.h

@@ -72,19 +72,19 @@ class SBFSubtarget : public SBFGenSubtargetInfo {
   // whether we should enable MCAsmInfo DwarfUsesRelocationsAcrossSections
   bool UseDwarfRIS;
 
-  // whether we are targeting SBFv2
-  bool IsSBFv2;
-
   // Whether to disable the negate (neg) instruction
   bool DisableNeg;
 
   // Whether to consider 'sub reg, imm' as 'reg = imm - reg', instead of 'reg =
   // reg - imm'.
   bool ReverseSubImm;
 
-  // wether we should use the LDDW instruction
+  // Whether we should use the LDDW instruction
   bool NoLddw;
 
+  // Whether to encode destination register in Callx's src field
+  bool CallxRegSrc;
+
 public:
   // This constructor initializes the data members to match that
   // of the specified triple.
@@ -104,10 +104,10 @@ class SBFSubtarget : public SBFGenSubtargetInfo {
   bool getHasDynamicFrames() const { return HasDynamicFrames; }
   bool getHasSdiv() const { return HasSdiv; }
   bool getUseDwarfRIS() const { return UseDwarfRIS; }
-  bool isSBFv2() const { return IsSBFv2; }
   bool getDisableNeg() const { return DisableNeg; }
   bool getReverseSubImm() const { return ReverseSubImm; }
   bool getNoLddw() const { return NoLddw; }
+  bool getCallXRegSrc() const { return CallxRegSrc; }
 
   const SBFInstrInfo *getInstrInfo() const override { return &InstrInfo; }
   const SBFFrameLowering *getFrameLowering() const override {

llvm/lib/Target/SBF/SBFTargetFeatures.td

@@ -0,0 +1,58 @@
+//===-- SBFTargetFeatures.td - Target Features for SBF Target ---------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the SBF target features in TableGen format.
+//
+//===----------------------------------------------------------------------===//
+
+def DummyFeature : SubtargetFeature<"dummy", "isDummyMode",
+                                    "true", "unused feature">;
+
+def ALU32 : SubtargetFeature<"alu32", "HasAlu32", "true",
+                             "Enable ALU32 instructions">;
+
+def DwarfRIS: SubtargetFeature<"dwarfris", "UseDwarfRIS", "true",
+                               "Disable MCAsmInfo DwarfUsesRelocationsAcrossSections">;
+
+def FeatureSolana : SubtargetFeature<"solana", "IsSolana", "true",
+                                     "Enable Solana extensions">;
+
+def FeatureDynamicFrames : SubtargetFeature<"dynamic-frames", "HasDynamicFrames", "true",
+                                            "Enable dynamic frames">;
+
+def FeatureSdiv : SubtargetFeature<"sdiv", "HasSdiv", "true",
+                                   "Enable native SBF_SDIV support">;
+
+def FeatureRelocAbs64 : SubtargetFeature<"reloc-abs64", "UseRelocAbs64", "true",
+                                   "Fix 64bit data relocations">;
+
+def FeatureStaticSyscalls : SubtargetFeature<"static-syscalls", "HasStaticSyscalls", "true",
+                                   "Marker feature used for conditional compilation">;
+
+def FeatureDisableNeg : SubtargetFeature<"no-neg", "DisableNeg", "true",
+                                    "Disable the neg instruction">;
+
+def FeatureReverseSubImm : SubtargetFeature<"reverse-sub", "ReverseSubImm", "true",
+                                    "Reverse the operands in the 'sub reg, imm' instruction">;
+
+def FeatureDisableLddw : SubtargetFeature<"no-lddw", "NoLddw", "true",
+                                    "Disable the lddw instruction">;
+
+def FeatureCallxRegSrc : SubtargetFeature<"callx-reg-src", "CallxRegSrc", "true",
+                                    "Encode Callx destination register in the src field">;
+
+class Proc<string Name, list<SubtargetFeature> Features>
+ : Processor<Name, NoItineraries, Features>;
+
+def : Proc<"generic", []>;
+def : Proc<"v1", []>;
+def : Proc<"v2", []>;
+def : Proc<"v3", []>;
+def : Proc<"probe", []>;
+def : Proc<"sbfv2", [FeatureSolana, FeatureDynamicFrames, FeatureSdiv, FeatureRelocAbs64, FeatureStaticSyscalls,
+                        FeatureDisableNeg, FeatureReverseSubImm, FeatureDisableLddw, FeatureCallxRegSrc]>;

llvm/test/CodeGen/SBF/callx.ll

@@ -1,12 +1,16 @@
-; RUN: llc < %s -march=sbf | FileCheck %s
+; RUN: llc < %s -march=sbf --show-mc-encoding \
+; RUN:      | FileCheck %s -check-prefixes=CHECK-v1
+; RUN: llc < %s -march=sbf --mcpu=sbfv2 --show-mc-encoding \
+; RUN:      | FileCheck %s -check-prefixes=CHECK-v2
 ; source:
 ;   int test(int (*f)(void)) { return f(); }
 
 ; Function Attrs: nounwind
 define dso_local i32 @test(i32 ()* nocapture %f) local_unnamed_addr #0 {
 entry:
   %call = tail call i32 %f() #1
-; CHECK: callx r{{[0-9]+}}
+; CHECK-v1: callx r{{[0-9]+}} # encoding: [0x8d,0x00,0x00,0x00,0x0{{[0-9]|a|b}},0x00,0x00,0x00]
+; CHECK-v2: callx r{{[0-9]+}} # encoding: [0x8d,0x{{[0-9]}}0,0x00,0x00,0x00,0x00,0x00,0x00]
   ret i32 %call
 }
 

llvm/test/MC/SBF/sbf-jmp.s

@@ -1,8 +1,13 @@
 # RUN: llvm-mc %s -triple=sbf-solana-solana --mcpu=sbfv2 --show-encoding \
 # RUN:     | FileCheck %s --check-prefix=CHECK-ASM-NEW
+# RUN: llvm-mc %s -triple=sbf-solana-solana --show-encoding \
+# RUN:     | FileCheck %s --check-prefix=CHECK-ASM-OLD
 # RUN: llvm-mc %s -triple=sbf-solana-solana --mcpu=sbfv2 -filetype=obj \
 # RUN:     | llvm-objdump -d -r - \
 # RUN:     | FileCheck --check-prefix=CHECK-OBJ-NEW %s
+# RUN: llvm-mc %s -triple=sbf-solana-solana -filetype=obj \
+# RUN:     | llvm-objdump -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-OBJ-OLD %s
 
 
 
@@ -215,7 +220,9 @@ jsle w5, -123, +8
 call 8
 
 # CHECK-OBJ-NEW: callx r4
-# CHECK-ASM-NEW: encoding: [0x8d,0x00,0x00,0x00,0x04,0x00,0x00,0x00]
+# CHECK-OBJ-OLD: callx r4
+# CHECK-ASM-NEW: encoding: [0x8d,0x40,0x00,0x00,0x00,0x00,0x00,0x00]
+# CHECK-ASM-OLD: encoding: [0x8d,0x00,0x00,0x00,0x04,0x00,0x00,0x00]
 callx r4
 
 # CHECK-OBJ-NEW: exit