Merge branch 'master' of github.com:parallella/oh

aolofsson · Apr 14, 2016 · 53dea82 · 53dea82
2 parents d237c17 + b70b9de
commit 53dea82
Show file tree

Hide file tree

Showing 31 changed files with 457 additions and 24 deletions.
diff --git a/src/common/hdl/oh_bin2onehot.v b/src/common/hdl/oh_bin2onehot.v
@@ -11,7 +11,7 @@ module oh_bin2onehot #(parameter DW = 32) // width of data inputs
  output [DW-1:0] out   // one hot output vector
  );
 
-   localparam NB = $clog2(DW);  // encoded bit width
+   parameter NB = $clog2(DW);  // encoded bit width
 
    integer 	  i;      
    reg [DW-1:0] 	  out;  

diff --git a/src/common/hdl/oh_debouncer.v b/src/common/hdl/oh_debouncer.v
@@ -18,7 +18,7 @@ module oh_debouncer #( parameter BOUNCE     = 100,    // bounce time (s)
    //################################
    //# wires/regs/ params
    //################################     
-   localparam integer CW  = $clog2(BOUNCE/CLKPERIOD);// counter width needed
+   parameter integer CW  = $clog2(BOUNCE/CLKPERIOD);// counter width needed
 
    //regs
    reg 	  noisy_reg;

diff --git a/src/common/hdl/oh_memory_dp.v b/src/common/hdl/oh_memory_dp.v
@@ -8,7 +8,8 @@
 module oh_memory_dp # (parameter DW    = 104,      //memory width
 		       parameter DEPTH = 32,       //memory depth
 		       parameter PROJ  = "",       //project name
-		       parameter MCW   = 8         //repair/config vector width
+		       parameter MCW   = 8,         //repair/config vector width
+		       parameter AW    = $clog2(DEPTH) // address bus width
 		       ) 
    (// Memory interface (dual port)
     input 	    wr_clk, //write clock
@@ -35,7 +36,6 @@ module oh_memory_dp # (parameter DW    = 104,      //memory width
     input [DW-1:0]  bist_din  // data input
     );
 
-   localparam AW      = $clog2(DEPTH);  // address bus width  
 
 `ifdef CFG_ASIC
    //NOT IMPLEMENTED...

diff --git a/src/common/hdl/oh_memory_ram.v b/src/common/hdl/oh_memory_ram.v
@@ -21,7 +21,7 @@ module oh_memory_ram  # (parameter DW    = 104,  //memory width
     input [DW-1:0]  wr_din // data input
     );
 
-   localparam AW      = $clog2(DEPTH);  // address bus width  
+   parameter AW      = $clog2(DEPTH);  // address bus width  
 
    reg [DW-1:0]        ram    [DEPTH-1:0];  
    reg [DW-1:0]        rd_dout;

diff --git a/src/common/hdl/oh_memory_sp.v b/src/common/hdl/oh_memory_sp.v
@@ -33,7 +33,7 @@ module oh_memory_sp  # (parameter DW    = 104,  //memory width
     input [DW-1:0]  bist_din  // data input
     );
 
-   localparam AW      = $clog2(DEPTH);  // address bus width  
+   parameter AW      = $clog2(DEPTH);  // address bus width  
 
 `ifdef CFG_ASIC
 

diff --git a/src/common/hdl/oh_par2ser.v b/src/common/hdl/oh_par2ser.v
@@ -24,7 +24,7 @@ module oh_par2ser #(parameter  PW   = 64, // parallel packet width
     );
 
    // parameters  
-   localparam CW   = $clog2(PW/SW);  // serialization factor (for counter)      
+   parameter CW   = $clog2(PW/SW);  // serialization factor (for counter)      
 
    reg [PW-1:0]    shiftreg;
    reg [CW-1:0]    count;

diff --git a/src/common/hdl/oh_ser2par.v b/src/common/hdl/oh_ser2par.v
@@ -16,7 +16,7 @@ module oh_ser2par #(parameter PW = 64, // parallel packet width
     input 	    shift      // shift the shifter
     );
 
-   localparam CW   = $clog2(PW/SW);  // serialization factor (for counter)
+   parameter CW   = $clog2(PW/SW);  // serialization factor (for counter)
 
    reg [PW-1:0]    dout;
    reg [CW-1:0]    count;

diff --git a/src/gpio/driver/gpio-generic.h b/src/gpio/driver/gpio-generic.h
@@ -5,7 +5,6 @@
 
 struct gpio_generic_dev {
 	volatile struct gpio_registers *regs;
-	uint64_t dircache;
 };
 
 __unused
@@ -16,14 +15,12 @@ static int _gpio_set_direction(struct gpio_generic_dev *dev, unsigned gpio,
 		return -EINVAL;
 
 	if (direction == GPIO_DIR_OUT)
-		dev->dircache |= (1ULL << gpio);
+		dev->regs->dir |= 1ULL << gpio;
 	else if (direction == GPIO_DIR_IN)
-		dev->dircache &= ~(1ULL << gpio);
+		dev->regs->dir &= ~(1ULL << gpio);
 	else
 		return -EINVAL;
 
-	dev->regs->dir = dev->dircache;
-
 	return 0;
 }
 

diff --git a/src/gpio/driver/gpio-simple.h b/src/gpio/driver/gpio-simple.h
@@ -18,7 +18,6 @@ static int gpio_init(gpio_dev_t *dev, void *arg)
 #endif
 
 	dev->regs = (struct gpio_registers *) arg;
-	dev->dircache = 0;
 
 	return 0;
 }

diff --git a/src/mio/hdl/mrx_protocol.v b/src/mio/hdl/mrx_protocol.v
@@ -12,7 +12,7 @@ module mrx_protocol (/*AUTOARG*/
    //parameters
    parameter  PW   = 104;               // packet width (core)
    parameter  NMIO = 8;                 // io packet width
-   localparam CW   = $clog2(2*PW/NMIO); // transfer count width
+   parameter  CW   = $clog2(2*PW/NMIO); // transfer count width
 
    //clock and reset
    input              rx_clk;        // rx clock

diff --git a/src/mio/hdl/mtx.v b/src/mio/hdl/mtx.v
@@ -16,7 +16,7 @@ module mtx (/*AUTOARG*/
    parameter NMIO       = 8;                 // IO data width
    parameter FIFO_DEPTH = 32;                // fifo depth  
    parameter TARGET     = "GENERIC";         // GENERIC,XILINX,ALTERA,ASIC
-   localparam CW        = $clog2(2*PW/NMIO); // transfer count width
+   parameter CW         = $clog2(2*PW/NMIO); // transfer count width
 
    //reset, clk, cfg
    input             clk;         // main core clock   

diff --git a/src/parallella/fpga/Makefile b/src/parallella/fpga/Makefile
@@ -3,8 +3,10 @@
 
 all:
 	make -C parallella_base/ all
-	make -C headless/ all
+	make -C headless_e16_z7010/ all
+	make -C headless_e16_z7020/ all
 
 clean:
 	make -C headless/ clean
-	make -C parallella_base/ clean
+	make -C headless_e16_z7010/ clean
+	make -C headless_e16_z7020/ clean
diff --git a/src/parallella/fpga/headless_e16_z7010-vs-z7020.diff b/src/parallella/fpga/headless_e16_z7010-vs-z7020.diff
@@ -0,0 +1,57 @@
+--- headless_e16_z7010/system_params.tcl	2016-03-11 12:19:17.200943709 +0100
++++ headless_e16_z7020/system_params.tcl	2015-11-09 19:23:07.699404317 +0100
+@@ -6,7 +6,7 @@
+ set projdir ./
+
+ #Device name
+-set partname "xc7z010clg400-1"
++set partname "xc7z020clg400-1"
+
+ #Paths to all IP blocks to use in Vivado "system.bd"
+
+@@ -19,4 +19,5 @@
+ set constraints_files [list \
+ 			   ../parallella_timing.xdc \
+ 			   ../parallella_io.xdc \
++			   ../parallella_7020_io.xdc \
+ 			  ]
+--- headless_e16_z7010/system_bd.tcl	2016-03-11 15:15:20.061868891 +0100
++++ headless_e16_z7020/system_bd.tcl	2016-03-11 15:59:44.849627304 +0100
+@@ -29,7 +29,7 @@
+
+ # If you do not already have a project created,
+ # you can create a project using the following command:
+-#    create_project project_1 myproj -part xc7z010clg400-1
++#    create_project project_1 myproj -part xc7z020clg400-1
+
+ # CHECKING IF PROJECT EXISTS
+ if { [get_projects -quiet] eq "" } {
+@@ -148,8 +148,8 @@
+   set cclk_n [ create_bd_port -dir O cclk_n ]
+   set cclk_p [ create_bd_port -dir O cclk_p ]
+   set chip_nreset [ create_bd_port -dir O chip_nreset ]
+-  set gpio_n [ create_bd_port -dir IO -from 11 -to 0 gpio_n ]
+-  set gpio_p [ create_bd_port -dir IO -from 11 -to 0 gpio_p ]
++  set gpio_n [ create_bd_port -dir IO -from 23 -to 0 gpio_n ]
++  set gpio_p [ create_bd_port -dir IO -from 23 -to 0 gpio_p ]
+   set hdmi_clk [ create_bd_port -dir O hdmi_clk ]
+   set hdmi_d [ create_bd_port -dir O -from 23 -to 8 hdmi_d ]
+   set hdmi_de [ create_bd_port -dir O hdmi_de ]
+@@ -186,7 +186,7 @@
+
+   # Create instance: parallella_base_0, and set properties
+   set parallella_base_0 [ create_bd_cell -type ip -vlnv www.parallella.org:user:parallella_base:1.0 parallella_base_0 ]
+-  set_property -dict [ list CONFIG.NGPIO {12}  ] $parallella_base_0
++  set_property -dict [ list CONFIG.NGPIO {24}  ] $parallella_base_0
+
+   # Create instance: proc_sys_reset_0, and set properties
+   set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ]
+--- headless_e16_z7010/build.sh	2016-03-11 12:16:03.342803755 +0100
++++ headless_e16_z7020/build.sh	2016-03-11 15:54:58.503321785 +0100
+@@ -2,5 +2,5 @@
+ rm system_wrapper.bit.bin bit2bin.bin
+ vivado -mode batch -source run.tcl
+ bootgen -image bit2bin.bif -split bin 
+-cp system_wrapper.bit.bin parallella_e16_headless_gpiose_7010.bit.bin
++cp system_wrapper.bit.bin parallella_e16_headless_gpiose_7020.bit.bin
+ #archive results based on time stamp
diff --git a/src/parallella/fpga/headless/Makefile → ...rallella/fpga/headless_e16_z7010/Makefile b/src/parallella/fpga/headless/Makefile → ...rallella/fpga/headless_e16_z7010/Makefile
@@ -15,7 +15,7 @@ M_FLIST += *.runs
 M_FLIST += *.srcs
 M_FLIST += *.sdk
 M_FLIST += .Xil
-M_FLIST += parallella.bit.bin
+M_FLIST += parallella_e16_headless_gpiose_7010.bit.bin
 M_FLIST += system_wrapper.bit.bin
 
 .PHONY: all clean
@@ -24,7 +24,7 @@ all: $(M_DEPS)
 	rm -f system_wrapper.bit.bin bit2bin.bin
 	$(M_VIVADO) run.tcl
 	bootgen -image bit2bin.bif -split bin
-	cp -f system_wrapper.bit.bin parallella.bit.bin
+	cp -f system_wrapper.bit.bin parallella_e16_headless_gpiose_7010.bit.bin
 
 clean:
 	rm -rf $(M_FLIST)
diff --git a/src/parallella/fpga/headless/bit2bin.bif → ...lella/fpga/headless_e16_z7010/bit2bin.bif b/src/parallella/fpga/headless/bit2bin.bif → ...lella/fpga/headless_e16_z7010/bit2bin.bif
diff --git a/src/parallella/fpga/headless/build.sh → ...rallella/fpga/headless_e16_z7010/build.sh b/src/parallella/fpga/headless/build.sh → ...rallella/fpga/headless_e16_z7010/build.sh
@@ -2,5 +2,5 @@
 rm system_wrapper.bit.bin bit2bin.bin
 vivado -mode batch -source run.tcl
 bootgen -image bit2bin.bif -split bin 
-cp system_wrapper.bit.bin parallella.bit.bin
+cp system_wrapper.bit.bin parallella_e16_headless_gpiose_7010.bit.bin
 #archive results based on time stamp
diff --git a/src/parallella/fpga/headless/dummy.elf → ...allella/fpga/headless_e16_z7010/dummy.elf b/src/parallella/fpga/headless/dummy.elf → ...allella/fpga/headless_e16_z7010/dummy.elf
diff --git a/src/parallella/fpga/headless/run.tcl → ...arallella/fpga/headless_e16_z7010/run.tcl b/src/parallella/fpga/headless/run.tcl → ...arallella/fpga/headless_e16_z7010/run.tcl