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spi: master doesn't transfer 2 MSB in data byte #84

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olajep opened this issue May 24, 2016 · 1 comment
Open

spi: master doesn't transfer 2 MSB in data byte #84

olajep opened this issue May 24, 2016 · 1 comment

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@olajep
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olajep commented May 24, 2016

Test case:
fclk0 = 25 MHz clkdiv=254 sclk = 100 kHz

  1. Master writes 0xff to SPI_USER0
  2. Master reads data from SPI_USER0

As seen in the waveform capture master does not transfer the two most significant bits in the data byte.
This does not seem to happen in simulation.

spi-high-bits-gone

waveform.vcd.txt

@olajep
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olajep commented May 24, 2016

It also drops the 2 MSB in the command byte.

olajep added a commit to olajep/oh that referenced this issue May 27, 2016
Use oh_fifo_cdc for XILINX target.

oh_fifo_sync does work in simulation but it does not work when
synthesizing in Vivado (see aolofsson#84).

This also includes a hack that forces the FIFO depth/width to 32/104
when TARGET is set to "XILINX" (only available FIFO IP atm.).

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
olajep added a commit to olajep/oh that referenced this issue May 27, 2016
Use oh_fifo_cdc for XILINX target.

oh_fifo_sync does work in simulation but it does not work when
synthesizing in Vivado (see aolofsson#84).

This also includes a hack that forces the FIFO depth/width to 32/104
when TARGET is set to "XILINX" (only available FIFO IP atm.).

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
olajep added a commit to olajep/oh that referenced this issue May 29, 2016
Use oh_fifo_cdc for XILINX target.

oh_fifo_sync does work in simulation but it does not work when
synthesizing in Vivado (see aolofsson#84).

This also includes a hack that forces the FIFO depth/width to 32/104
when TARGET is set to "XILINX" (only available FIFO IP atm.).

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
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