riscv64: fix fenv handling
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unicornx
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Mar 10, 2022
unicornx
reviewed
Mar 10, 2022
unicornx
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Mar 10, 2022
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From your changes and test result, I think for this issue, we'd better catch up with RVI upstream for fenv related files. |
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Addressed comments. |
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tests/fenv_test: add RISC-V to the RISC test group, so that fesetexcept will be tested according to RISC architectures
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This pull request fixes several issues with
fenvhandling and should close aosp-riscv/working-group#39.Issues with
fesetenvThere was a typo in
fesetenvthat prevented thefcsrto be set correctly. The typo has been corrected.Issues with
fesetexceptfesetexceptshould return-1when the architecture does not support masking FPU exception vectors.Issues with
tests/fenv_test.cppSince RISC-V is a RISC architecture, it should be tested like other RISC architecture:
fesetexceptshould return-1(indicates the platforms does not support it), andfegetexceptshould always return0.