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ARROW-17440: [C++] Support RISC-V architecture #13902

Merged
merged 2 commits into from
Aug 17, 2022
Merged

ARROW-17440: [C++] Support RISC-V architecture #13902

merged 2 commits into from
Aug 17, 2022

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felixonmars
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Signed-off-by: Felix Yan felixonmars@archlinux.org

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https://issues.apache.org/jira/browse/ARROW-17440

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⚠️ Ticket has not been started in JIRA, please click 'Start Progress'.

@cyb70289
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Did a quick test on x86 host with qemu and riscv ubuntu image. MemoryAdviseWillNeed utility test failed, probably because madvise(WILLNEED) doesn't work under qemu.

felixonmars and others added 2 commits August 17, 2022 02:45
@felixonmars @cyb70289
ARROW-17440: [C++] Support RISC-V architecture
27e49fe 
Signed-off-by: Felix Yan <felixonmars@archlinux.org>
@cyb70289
fix x86 arch detection
48ad16d
@cyb70289 cyb70289 requested a review from pitrou August 17, 2022 04:12
pitrou
pitrou reviewed Aug 17, 2022
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cpp/cmake_modules/SetupCxxFlags.cmake
else()
set(ARROW_CPU_FLAG "x86")
message(FATAL_ERROR "Unknown system processor")
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Don't we want to be open-ended instead?

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Suggested change
message(FATAL_ERROR "Unknown system processor")
message(WARNING "Unknown system processor")

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My concern is if some patterns are missed in MATCHES list, CPU specific settings below may be skipped accidentally if user doesn't notice the message, e.g, without enabling SIMD flags.

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Hmm, fair enough.

pitrou
pitrou approved these changes Aug 17, 2022
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LGTM. Thanks @felixonmars and @cyb70289 !

@pitrou pitrou merged commit 050876c into apache:master Aug 17, 2022
@felixonmars felixonmars deleted the riscv branch August 17, 2022 08:55
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ursabot commented Aug 17, 2022

Benchmark runs are scheduled for baseline = 9d1bbaf and contender = 050876c. 050876c is a master commit associated with this PR. Results will be available as each benchmark for each run completes.
Conbench compare runs links:
[Finished ⬇️0.0% ⬆️0.0%] ec2-t3-xlarge-us-east-2
[Failed ⬇️0.0% ⬆️0.0%] test-mac-arm
[Failed ⬇️0.0% ⬆️0.0%] ursa-i9-9960x
[Finished ⬇️0.0% ⬆️0.0%] ursa-thinkcentre-m75q
Buildkite builds:
[Finished] 050876c5 ec2-t3-xlarge-us-east-2
[Failed] 050876c5 test-mac-arm
[Failed] 050876c5 ursa-i9-9960x
[Finished] 050876c5 ursa-thinkcentre-m75q
[Finished] 9d1bbaff ec2-t3-xlarge-us-east-2
[Finished] 9d1bbaff test-mac-arm
[Failed] 9d1bbaff ursa-i9-9960x
[Finished] 9d1bbaff ursa-thinkcentre-m75q
Supported benchmarks:
ec2-t3-xlarge-us-east-2: Supported benchmark langs: Python, R. Runs only benchmarks with cloud = True
test-mac-arm: Supported benchmark langs: C++, Python, R
ursa-i9-9960x: Supported benchmark langs: Python, R, JavaScript
ursa-thinkcentre-m75q: Supported benchmark langs: C++, Java

@felixonmars
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Did a quick test on x86 host with qemu and riscv ubuntu image. MemoryAdviseWillNeed utility test failed, probably because madvise(WILLNEED) doesn't work under qemu.

MemoryAdviseWillNeed is passing here on VisionFive v1 development board. However, I got multiple failures in arrow-flight-test like:

[ RUN      ] GrpcDoPutTest.TestFloats
/build/arrow/src/apache-arrow-8.0.1/cpp/src/arrow/flight/test_definitions.cc:690: Failure
Failed
'writer->Close()' failed with Invalid: Expected app_metadata to be foo bar but got \0\0\0\0\0\0\0. gRPC client debug context: UNKNOWN:Error received from peer ipv4:127.0.0.1:40397 {grpc_message:"Expected app_metadata to be foo bar but got \x00\x00\x00\x00\x00\x00\x00", grpc_status:3, created_time:"2022-08-17T15:58:30.647837384+03:00"}. Client context: OK
[  FAILED  ] GrpcDoPutTest.TestFloats (16 ms)

Retried a few times ending up with different subset of the test suite failing. I'm testing against arrow 8.0.1 though, not sure if they are already fixed.

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pitrou commented Aug 17, 2022

@felixonmars Would be nice if you could test with git master. If the failure still occurs there, feel free to open a JIRA :-)

felixonmars added a commit to felixonmars/archriscv-packages that referenced this pull request Aug 19, 2022
@felixonmars
addpatch: arrow
7611acb 
- LTO is disabled for similar reason as #1620

- The `-DARROW_CPU_FLAG=riscv64` is no longer needed in a future version
  containing apache/arrow#13902

- Added to qemu-user-blacklist because QEMU doesn't support
  madvise(WILLNEED) properly (this includes qemu-system, actually)

- `nocheck` is needed for now as `arrow-flight-test` is failing with the
  current version but not on git master. Recheck on next release!
@felixonmars felixonmars mentioned this pull request Aug 19, 2022
Merged
felixonmars added a commit to felixonmars/archriscv-packages that referenced this pull request Aug 20, 2022
@felixonmars
addpatch: arrow
e41bb9d 
- LTO is disabled for similar reason as #1620

- The `-DARROW_CPU_FLAG=riscv64` is no longer needed in a future version
  containing apache/arrow#13902

- Added to qemu-user-blacklist because QEMU doesn't support
  madvise(WILLNEED) properly (this includes qemu-system, actually)

- `nocheck` is needed for now as `arrow-flight-test` is failing with the
  current version but not on git master. Recheck on next release!
zagto pushed a commit to zagto/arrow that referenced this pull request Oct 7, 2022
@felixonmars @zagto
ARROW-17440: [C++] Support RISC-V architecture (apache#13902)
52eaedb 
Signed-off-by: Felix Yan <felixonmars@archlinux.org>

Lead-authored-by: Yibo Cai <yibo.cai@arm.com>
Co-authored-by: Felix Yan <felixonmars@archlinux.org>
Signed-off-by: Antoine Pitrou <antoine@python.org>
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