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esp32: Re-organize the interrupt handling process to correctly handle the SMP case #4388
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@masayuki2009 this is a draft just because I might create separate PRs for the different changes if required. Otherwise, the change is ready. It implements enabling/disabling interrupts using the Interrupt Matrix. |
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Hmm, I tried esp32-devkitc:wapi_smp but I was not able to connect to my Wi-Fi access point.
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@masayuki2009 thanks for testing, let me check. |
@Ouss4
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@masayuki2009 enabling the Wi-fi interrupt at the core level was lost in the middle of my rebasing. I added it again. Please check. Since now we control peripheral interrupt only based on the Interrupt Matrix, the in-core interrupts has to be enabled at start-up. This is done during the setup of an interrupt, but since Wi-fi is setup with the external library, it has to be handled separately. |
@Ouss4 |
@masayuki2009 @gustavonihei I'm keeping the commits as they are to ease reviewing. Once that's done, I'll squash some of them. |
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LGTM
@Ouss4
For example, if the code is not atomic, the currently running CPU would be switched to another CPU after calling up_cpu_index(). So please be careful when calling up_cpu_index(). |
@masayuki2009 if I'm not mistaken all of those calls are within a critical section. I'll check again tomorrow from my computer. |
@Ouss4 |
interrupt. That function will have a parameter to decide whether to allocate a level sensitive interrupt or an edge sensitive interrupt. All the drivers are also updated with this API change. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
Allocating and attaching interrupts were both exported outside, however these two move hand in hand and we don't have to expose these details. Also, the parameters passed are saved and will be used to retrieve information about the interrupt and the attached peripheral. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
address of a peripheral. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
They do the same thing (manipulate interrupts) keeping them separated was making things harder. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
only inside this file. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
xtensa/include/irq.h Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
Matrix. This allows manipulating interrupts from both CPUs. Internal interrupts however, still need to be disabled/enabled by each CPU. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
status of the interrupt (enabled/disabled). Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
@masayuki2009 I have checked that all the calls are from within a critical section. There is only the emac driver initialization and the serial DMA initialization that don't explicitly call I have also done some squashing. |
Summary
This PR has 3 major changes:
INTENABLE
register, the Interrupt Matrix can be accessed by both CPUs. Hence, manipulating interrupts can be done without inter-CPU calls.Impact
ESP32 chip.
Testing
All of the in-tree ESP32 defconfigs were tested.