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arm/cortex-[a|r]/thumb: force assembler files to be interpreted as Thumb code #7751

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merged 3 commits into from Dec 1, 2022

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@anchao anchao commented Dec 1, 2022

Summary

  1. arm/cortex-[a|r]/thumb: force assembler files to be interpreted as Thumb code

The option '-mthumb' is only valid for C source files and it is not passed to the assembler.

If 'thumb' is not considered in some assembly projects, the system will generate
'undefined instructions' when running incompatible instruction:

arm_undefinedinsn: Undefined instruction at 0x380cfc98

This assembly file should be compiled with .thumb but it doesn't:

380cfc90 <hobot_i8_i32_gemm_nn_m4_n8_neon>:
380cfc90: e92d4ff0  push  {r4, r5, r6, r7, r8, r9, sl, fp, lr}
380cfc94: ed2d8b10  vpush {d8-d15}
380cfc98: e59d4064  ldr r4, [sp, #100]  ; 0x64   <-- Undefined instruction
380cfc9c: e59d5068  ldr r5, [sp, #104]  ; 0x68
380cfca0: e59d606c  ldr r6, [sp, #108]  ; 0x6c
380cfca4: e59d7070  ldr r7, [sp, #112]  ; 0x70
380cfca8: e1a08120  lsr r8, r0, #2
380cfcac: e1a091a1  lsr r9, r1, #3
380cfcb0: e1a0a122  lsr sl, r2, #2

After enable thumb:
.syntax unified
.thumb
or
-Wa,-mthumb

.Lhobot_i8_i32_gemm_nn_m4_n8_neon:
38001100: e92d 4ff0   stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
38001104: ed2d 8b10   vpush {d8-d15}
38001108: 9c19        ldr r4, [sp, #100]  ; 0x64
3800110a: 9d1a        ldr r5, [sp, #104]  ; 0x68
3800110c: 9e1b        ldr r6, [sp, #108]  ; 0x6c
3800110e: 9f1c        ldr r7, [sp, #112]  ; 0x70
38001110: ea4f 0890   mov.w r8, r0, lsr #2
38001114: ea4f 09d1   mov.w r9, r1, lsr #3
38001118: ea4f 0a92   mov.w sl, r2, lsr #2

This commit will enable the thumb option of the assembly file by default,
so that when compiling the assembly file, the machine code and the system will be in a consistent state.


https://gcc.gnu.org/onlinedocs/gcc-4.5.2/gcc/ARM-Options.html

GCC Manual:
-mthumb
  Generate code for the Thumb instruction set. The default is to use the 32-bit ARM
  instruction set. This option automatically enables either 16-bit Thumb-1 or mixed 16/32-bit
  Thumb-2 instructions based on the -mcpu=name and -march=name options.

  ** This option is not passed to the assembler. **
  ** If you want to force assembler files to be interpreted as Thumb code,
     either add a `.thumb' directive to the source or pass the -mthumb option
     directly to the assembler by prefixing it with -Wa. **
  1. arm/thumb: outputs an implicit IT block to avoid build break

Fix build break on thumb2 mode:

opus/celt/arm/celt_pitch_xcorr_arm-gnu.S: Assembler messages:
opus/celt/arm/celt_pitch_xcorr_arm-gnu.S:146: Error: thumb conditional instruction should be in IT block -- `movle pc,lr'

Reference:
https://developer.arm.com/documentation/100067/0612/armclang-Command-line-Options/-mimplicit-it

In A32 code, the integrated assembler accepts all conditional instructions
without giving an error or warning. In T32 code, the integrated assembler
outputs an implicit IT block when there is a conditional instruction
without an enclosing IT block. The integrated assembler does not give an
error or warning about this.

Signed-off-by: chao an anchao@xiaomi.com

Impact

Testing

…umb code

The option '-mthumb' is only valid for C source files and it is not passed to the assembler.

If 'thumb' is not considered in some assembly projects, the system will generate
'undefined instructions' when running incompatible instruction:

arm_undefinedinsn: Undefined instruction at 0x380cfc98

This assembly file should be compiled with .thumb but it doesn't:

380cfc90 <hobot_i8_i32_gemm_nn_m4_n8_neon>:
380cfc90: e92d4ff0  push  {r4, r5, r6, r7, r8, r9, sl, fp, lr}
380cfc94: ed2d8b10  vpush {d8-d15}
380cfc98: e59d4064  ldr r4, [sp, apache#100]  ; 0x64   <-- Undefined instruction
380cfc9c: e59d5068  ldr r5, [sp, apache#104]  ; 0x68
380cfca0: e59d606c  ldr r6, [sp, apache#108]  ; 0x6c
380cfca4: e59d7070  ldr r7, [sp, apache#112]  ; 0x70
380cfca8: e1a08120  lsr r8, r0, #2
380cfcac: e1a091a1  lsr r9, r1, #3
380cfcb0: e1a0a122  lsr sl, r2, #2

After enable thumb:
  .syntax unified
  .thumb
or
  -Wa,-mthumb

.Lhobot_i8_i32_gemm_nn_m4_n8_neon:
38001100: e92d 4ff0   stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
38001104: ed2d 8b10   vpush {d8-d15}
38001108: 9c19        ldr r4, [sp, apache#100]  ; 0x64
3800110a: 9d1a        ldr r5, [sp, apache#104]  ; 0x68
3800110c: 9e1b        ldr r6, [sp, apache#108]  ; 0x6c
3800110e: 9f1c        ldr r7, [sp, apache#112]  ; 0x70
38001110: ea4f 0890   mov.w r8, r0, lsr #2
38001114: ea4f 09d1   mov.w r9, r1, lsr #3
38001118: ea4f 0a92   mov.w sl, r2, lsr #2

This commit will enable the thumb option of the assembly file by default,
so that when compiling the assembly file, the machine code and the system will be in a consistent state.

----------------------------------------------------------------
https://gcc.gnu.org/onlinedocs/gcc-4.5.2/gcc/ARM-Options.html

GCC Manual:
-mthumb
  Generate code for the Thumb instruction set. The default is to use the 32-bit ARM
  instruction set. This option automatically enables either 16-bit Thumb-1 or mixed 16/32-bit
  Thumb-2 instructions based on the -mcpu=name and -march=name options.

  ** This option is not passed to the assembler. **
  ** If you want to force assembler files to be interpreted as Thumb code,
     either add a `.thumb' directive to the source or pass the -mthumb option
     directly to the assembler by prefixing it with -Wa. **

Signed-off-by: chao an <anchao@xiaomi.com>
Fix build break on thumb2 mode:
opus/celt/arm/celt_pitch_xcorr_arm-gnu.S: Assembler messages:
opus/celt/arm/celt_pitch_xcorr_arm-gnu.S:146: Error: thumb conditional instruction should be in IT block -- `movle pc,lr'

Reference:
https://developer.arm.com/documentation/100067/0612/armclang-Command-line-Options/-mimplicit-it

In A32 code, the integrated assembler accepts all conditional instructions
without giving an error or warning. In T32 code, the integrated assembler
outputs an implicit IT block when there is a conditional instruction
without an enclosing IT block. The integrated assembler does not give an
error or warning about this.

Signed-off-by: chao an <anchao@xiaomi.com>
@pkarashchenko pkarashchenko merged commit 77aede7 into apache:master Dec 1, 2022
@jerpelea jerpelea added this to To-Add in Release Notes - 12.0.0 Dec 29, 2022
@jerpelea jerpelea moved this from To-Add to Added in Release Notes - 12.0.0 Jan 9, 2023
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3 participants