arm/armv7-a/r: set the default CPU mode to System

In SVC mode, the banked register will be inconsistent with the user mode register:

arch/arm/src/armv7-a/arm_vectors.S

 276   .globl  arm_syscall
 277   .globl  arm_vectorsvc
 278   .type arm_vectorsvc, %function
 279
 280 arm_vectorsvc:
...
 286   sub   sp, sp, #XCPTCONTEXT_SIZE        // < SVC mode SP
...
 308   stmia   r0, {r13, r14}^                // < USR mode SP/LR
...

[    2.200000] [ 4] [ ALERT] SYSCALL Entry: regs: 0x80202708 cmd: 4
[    2.200000] [ 4] [ ALERT]   R0: 00000004 80001229 00000001 80202018 00000000 00000000 00000000 802027d0
[    2.200000] [ 4] [ ALERT]   R8: 00000000 00000000 00000000 00000000 00000000 802027d0 1080f710 1080f710
[    2.200000] [ 4] [ ALERT] CPSR: 00000073
[    2.200000] [ 4] [ ALERT] SYSCALL Exit: regs: 0x80202708
[    2.200000] [ 4] [ ALERT]   R0: 1 80202018 1 80202018 0 0 0 802027d0
[    2.200000] [ 4] [ ALERT]   R8: 0 0 0 0 0 802027d0 1080f710 80001229
[    2.200000] [ 4] [ ALERT] CPSR: 00000070

SVC SP is 0x80202708
USR SP is 0x802027d0
0x802027d0 - 0x80202708 should be XCPTCONTEXT_SIZE

[    2.200000] [ 4] [ ALERT] SYSCALL Entry: regs: 0x80202708 cmd: 51
[    2.200000] [ 4] [ ALERT]   R0: 00000033 00000000 80202780 00000000 00000000 00000000 00000000 80202710
[    2.200000] [ 4] [ ALERT]   R8: 00000000 00000000 00000000 00000000 00000000 80202710 800039d5 800039b2
[    2.200000] [ 4] [ ALERT] CPSR: 00000070
[    2.200000] [ 4] [ ALERT] SYSCALL Exit: regs: 0x80202708
[    2.200000] [ 4] [ ALERT]   R0: 2b 0 80202780 0 0 0 0 80202710
[    2.200000] [ 4] [ ALERT]   R8: 0 0 0 0 0 10843d80 800039d5 10801425
[    2.200000] [ 4] [ ALERT] CPSR: 00000073

SVC SP is 0x80202708
USR SP is 0x80202710
SP overlap in SVC and USR mode

This commit change the default CPU mode to System and ensure the consistency of SP/LR in USR/SYS mode during syscall.

Signed-off-by: chao.an <anchao@xiaomi.com>

arch/arm/src/arm/arm_head.S

@@ -220,9 +220,9 @@
 	.type	__start, #function
 
 __start:
-	/* Make sure that we are in SVC mode with all IRQs disabled */
+	/* Make sure that we are in SYS mode with all IRQs disabled */
 
-	mov		r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
+	mov		r0, #(PSR_MODE_SYS | PSR_I_BIT | PSR_F_BIT)
 	msr		cpsr_c, r0
 
 	/* Initialize DRAM using a macro provided by board-specific logic */

arch/arm/src/arm/arm_initialstate.c

@@ -111,7 +111,7 @@ void up_initial_state(struct tcb_s *tcb)
     {
       /* It is a kernel thread.. set supervisor mode */
 
-      cpsr               = PSR_MODE_SVC | PSR_F_BIT;
+      cpsr               = PSR_MODE_SYS | PSR_F_BIT;
     }
   else
     {
@@ -124,7 +124,7 @@ void up_initial_state(struct tcb_s *tcb)
    * supervisor-mode.
    */
 
-  cpsr                   = PSR_MODE_SVC | PSR_F_BIT;
+  cpsr                   = PSR_MODE_SYS | PSR_F_BIT;
 #endif
 
   /* Enable or disable interrupts, based on user configuration */

arch/arm/src/arm/arm_nommuhead.S

@@ -58,7 +58,7 @@ __start:
 
 	/* First, setup initial processor mode */
 
-	mov		r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT )
+	mov		r0, #(PSR_MODE_SYS | PSR_I_BIT | PSR_F_BIT )
 	msr		cpsr, r0
 
 	/* Setup system stack (and get the BSS range) */

arch/arm/src/arm/arm_schedulesigaction.c

@@ -130,7 +130,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
                */
 
               CURRENT_REGS[REG_PC]   = (uint32_t)arm_sigdeliver;
-              CURRENT_REGS[REG_CPSR] = PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT;
+              CURRENT_REGS[REG_CPSR] = PSR_MODE_SYS | PSR_I_BIT | PSR_F_BIT;
 
               /* And make sure that the saved context in the TCB
                * is the same as the interrupt return context.
@@ -162,7 +162,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
            */
 
           tcb->xcp.regs[REG_PC]      = (uint32_t)arm_sigdeliver;
-          tcb->xcp.regs[REG_CPSR]    = PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT;
+          tcb->xcp.regs[REG_CPSR]    = PSR_MODE_SYS | PSR_I_BIT | PSR_F_BIT;
         }
     }
 }