add support for PolarFire SoC and icicle board

Co-authored-by: Eero Nurkkala <eero.nurkkala@offcode.fi>

arch/risc-v/Kconfig

@@ -60,6 +60,13 @@ config ARCH_CHIP_C906
 	---help---
 		THEAD C906 processor (RISC-V 64bit core with GCVX extensions).
 
+config ARCH_CHIP_MPFS
+        bool "MicroChip Polarfire (MPFS)"
+        select ARCH_RV64GC
+        select ARCH_HAVE_MPU
+        ---help---
+		MicroChip Polarfire processor (RISC-V 64bit core with GCVX extensions).
+
 config ARCH_CHIP_RISCV_CUSTOM
 	bool "Custom RISC-V chip"
 	select ARCH_CHIP_CUSTOM
@@ -97,6 +104,7 @@ config ARCH_CHIP
 	default "bl602"		if ARCH_CHIP_BL602
 	default "esp32c3"	if ARCH_CHIP_ESP32C3
 	default "c906"		if ARCH_CHIP_C906
+	default "mpfs"		if ARCH_CHIP_MPFS
 
 if ARCH_RV32IM
 source arch/risc-v/src/rv32im/Kconfig
@@ -122,4 +130,7 @@ endif
 if ARCH_CHIP_C906
 source arch/risc-v/src/c906/Kconfig
 endif
+if ARCH_CHIP_MPFS
+source arch/risc-v/src/mpfs/Kconfig
+endif
 endif

arch/risc-v/include/mpfs/chip.h

@@ -0,0 +1,34 @@
+/****************************************************************************
+ * arch/risc-v/include/mpfs/chip.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_INCLUDE_MPFS_CHIP_H
+#define __ARCH_RISCV_INCLUDE_MPFS_CHIP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <stdint.h>
+
+#include <arch/irq.h>
+
+#endif /* __ARCH_RISCV_INCLUDE_MPFS_CHIP_H */

arch/risc-v/src/mpfs/Kconfig

@@ -0,0 +1,93 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+
+comment "Polarfire Configuration Options"
+
+config MPFS_ENABLE_DPFPU
+	bool "MPFS DP_FPU Support"
+	default n
+	select ARCH_HAVE_FPU
+	select ARCH_HAVE_DPFPU
+	---help---
+		Enable the RISC-V Double-Precision Floating Point Unit (DP-FPU).
+
+menu "MPFS Peripheral Support"
+
+# These "hidden" settings determine whether a peripheral option is available
+# for the selected MCU
+
+config MPFS_HAVE_UART0
+	bool
+	default n
+	select UART0_SERIALDRIVER
+	select ARCH_HAVE_SERIAL_TERMIOS
+
+config MPFS_HAVE_UART1
+	bool
+	default n
+	select UART1_SERIALDRIVER
+	select ARCH_HAVE_SERIAL_TERMIOS
+
+config MPFS_HAVE_UART2
+	bool
+	default n
+	select UART2_SERIALDRIVER
+	select ARCH_HAVE_SERIAL_TERMIOS
+
+config MPFS_HAVE_UART3
+	bool
+	default n
+	select UART3_SERIALDRIVER
+	select ARCH_HAVE_SERIAL_TERMIOS
+
+config MPFS_HAVE_UART4
+	bool
+	default n
+	select UART4_SERIALDRIVER
+	select ARCH_HAVE_SERIAL_TERMIOS
+
+# These are the peripheral selections proper
+
+config MPFS_UART0
+	bool "UART 0"
+	default n
+	select ARCH_HAVE_UART0
+	select ARCH_HAVE_SERIAL_TERMIOS
+	select MPFS_HAVE_UART0
+
+config MPFS_UART1
+	bool "UART 1"
+	default n
+	select ARCH_HAVE_UART1
+	select ARCH_HAVE_SERIAL_TERMIOS
+	select MPFS_HAVE_UART1
+
+config MPFS_UART2
+	bool "UART 2"
+	default n
+	select ARCH_HAVE_UART2
+	select ARCH_HAVE_SERIAL_TERMIOS
+	select MPFS_HAVE_UART2
+
+config MPFS_UART3
+	bool "UART 3"
+	default n
+	select ARCH_HAVE_UART3
+	select ARCH_HAVE_SERIAL_TERMIOS
+	select MPFS_HAVE_UART3
+
+config MPFS_UART4
+	bool "UART 4"
+	default n
+	select ARCH_HAVE_UART4
+	select ARCH_HAVE_SERIAL_TERMIOS
+	select MPFS_HAVE_UART4
+
+endmenu
+
+menu "MPFS Others"
+
+
+endmenu

arch/risc-v/src/mpfs/Make.defs

@@ -0,0 +1,63 @@
+############################################################################
+# arch/risc-v/src/mpfs/Make.defs
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements.  See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership.  The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License.  You may obtain a copy of the License at
+#
+#   http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+# Specify our HEAD assembly file.  This will be linked as
+# the first object file, so it will appear at address 0
+HEAD_ASRC = mpfs_vectors.S
+
+# Specify our general Assembly files
+CHIP_ASRCS = mpfs_head.S
+
+# Specify C code within the common directory to be included
+CMN_CSRCS  += riscv_initialize.c riscv_swint.c
+CMN_CSRCS  += riscv_createstack.c riscv_exit.c riscv_fault.c
+CMN_CSRCS  += riscv_assert.c riscv_blocktask.c riscv_copystate.c riscv_initialstate.c
+CMN_CSRCS  += riscv_interruptcontext.c riscv_modifyreg32.c riscv_puts.c
+CMN_CSRCS  += riscv_releasepending.c riscv_reprioritizertr.c
+CMN_CSRCS  += riscv_releasestack.c riscv_stackframe.c riscv_schedulesigaction.c
+CMN_CSRCS  += riscv_sigdeliver.c riscv_unblocktask.c riscv_usestack.c
+CMN_CSRCS  += riscv_mdelay.c riscv_copyfullstate.c
+
+ifeq ($(CONFIG_STACK_COLORATION),y)
+CMN_CSRCS += riscv_checkstack.c
+endif
+
+ifeq ($(CONFIG_ARCH_FPU),y)
+CMN_ASRCS  += riscv_fpu.S
+endif
+
+ifeq ($(CONFIG_ARCH_HAVE_VFORK),y)
+CMN_CSRCS  += riscv_vfork.c
+endif
+
+# Specify our C code within this directory to be included
+CHIP_CSRCS  = mpfs_allocateheap.c mpfs_clockconfig.c
+CHIP_CSRCS += mpfs_idle.c mpfs_irq.c mpfs_irq_dispatch.c
+CHIP_CSRCS += mpfs_lowputc.c mpfs_serial.c
+CHIP_CSRCS += mpfs_start.c mpfs_timerisr.c
+CHIP_CSRCS += mpfs_gpio.c
+
+ifeq ($(CONFIG_BUILD_PROTECTED),y)
+CMN_CSRCS  += riscv_task_start.c riscv_pthread_start.c
+CMN_CSRCS  += riscv_signal_dispatch.c riscv_pmp.c
+CMN_UASRCS += riscv_signal_handler.S
+
+CHIP_CSRCS += mpfs_userspace.c
+endif

arch/risc-v/src/mpfs/chip.h

@@ -0,0 +1,32 @@
+/****************************************************************************
+ * arch/risc-v/src/mpfs/chip.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_MPFS_CHIP_H
+#define __ARCH_RISCV_SRC_MPFS_CHIP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "mpfs_memorymap.h"
+
+#endif /* __ARCH_RISCV_SRC_MPFS_CHIP_H */

arch/risc-v/src/mpfs/hardware/mpfs_clint.h

@@ -0,0 +1,42 @@
+/****************************************************************************
+ * arch/risc-v/src/mpfs/hardware/mpfs_clint.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_CLINT_H
+#define __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_CLINT_H
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define MPFS_CLINT_MSIP0     (MPFS_CLINT_BASE + 0x0000)
+#define MPFS_CLINT_MSIP1     (MPFS_CLINT_BASE + 0x0004)
+#define MPFS_CLINT_MSIP2     (MPFS_CLINT_BASE + 0x0008)
+#define MPFS_CLINT_MSIP3     (MPFS_CLINT_BASE + 0x000C)
+#define MPFS_CLINT_MSIP4     (MPFS_CLINT_BASE + 0x0010)
+
+#define MPFS_CLINT_MTIMECMP0 (MPFS_CLINT_BASE + 0x4000)
+#define MPFS_CLINT_MTIMECMP1 (MPFS_CLINT_BASE + 0x4008)
+#define MPFS_CLINT_MTIMECMP2 (MPFS_CLINT_BASE + 0x4010)
+#define MPFS_CLINT_MTIMECMP3 (MPFS_CLINT_BASE + 0x4018)
+#define MPFS_CLINT_MTIMECMP4 (MPFS_CLINT_BASE + 0x4020)
+
+#define MPFS_CLINT_MTIME     (MPFS_CLINT_BASE + 0xbff8)
+
+#endif /* __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_CLINT_H */

arch/risc-v/src/mpfs/hardware/mpfs_gpio.h

@@ -0,0 +1,96 @@
+/****************************************************************************
+ * arch/risc-v/src/mpfs/hardware/mpfs_gpio.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_GPIO_H
+#define __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_GPIO_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include "hardware/mpfs_memorymap.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define MPFS_GPIO_CONFIG_0_OFFSET     0x0000 /* GPIO Config 0 */
+#define MPFS_GPIO_CONFIG_1_OFFSET     0x0004 /* GPIO Config 1 */
+#define MPFS_GPIO_CONFIG_2_OFFSET     0x0008 /* GPIO Config 2 */
+#define MPFS_GPIO_CONFIG_3_OFFSET     0x000C /* GPIO Config 3 */
+#define MPFS_GPIO_CONFIG_4_OFFSET     0x0010 /* GPIO Config 4 */
+#define MPFS_GPIO_CONFIG_5_OFFSET     0x0014 /* GPIO Config 5 */
+#define MPFS_GPIO_CONFIG_6_OFFSET     0x0018 /* GPIO Config 6 */
+#define MPFS_GPIO_CONFIG_7_OFFSET     0x001C /* GPIO Config 7 */
+#define MPFS_GPIO_CONFIG_8_OFFSET     0x0020 /* GPIO Config 8 */
+#define MPFS_GPIO_CONFIG_9_OFFSET     0x0024 /* GPIO Config 9 */
+#define MPFS_GPIO_CONFIG_10_OFFSET    0x0028 /* GPIO Config 10 */
+#define MPFS_GPIO_CONFIG_11_OFFSET    0x002C /* GPIO Config 11 */
+#define MPFS_GPIO_CONFIG_12_OFFSET    0x0020 /* GPIO Config 12 */
+#define MPFS_GPIO_CONFIG_13_OFFSET    0x0024 /* GPIO Config 13 */
+#define MPFS_GPIO_CONFIG_14_OFFSET    0x0028 /* GPIO Config 14 */
+#define MPFS_GPIO_CONFIG_15_OFFSET    0x002C /* GPIO Config 15 */
+#define MPFS_GPIO_CONFIG_16_OFFSET    0x0040 /* GPIO Config 16 */
+#define MPFS_GPIO_CONFIG_17_OFFSET    0x0044 /* GPIO Config 17 */
+#define MPFS_GPIO_CONFIG_18_OFFSET    0x0048 /* GPIO Config 18 */
+#define MPFS_GPIO_CONFIG_19_OFFSET    0x004C /* GPIO Config 19 */
+#define MPFS_GPIO_CONFIG_20_OFFSET    0x0050 /* GPIO Config 20 */
+#define MPFS_GPIO_CONFIG_21_OFFSET    0x0054 /* GPIO Config 21 */
+#define MPFS_GPIO_CONFIG_22_OFFSET    0x0058 /* GPIO Config 22 */
+#define MPFS_GPIO_CONFIG_23_OFFSET    0x005C /* GPIO Config 23 */
+#define MPFS_GPIO_CONFIG_24_OFFSET    0x0060 /* GPIO Config 24 */
+#define MPFS_GPIO_CONFIG_25_OFFSET    0x0064 /* GPIO Config 25 */
+#define MPFS_GPIO_CONFIG_26_OFFSET    0x0068 /* GPIO Config 26 */
+#define MPFS_GPIO_CONFIG_27_OFFSET    0x006C /* GPIO Config 27 */
+#define MPFS_GPIO_CONFIG_28_OFFSET    0x0070 /* GPIO Config 28 */
+#define MPFS_GPIO_CONFIG_29_OFFSET    0x0074 /* GPIO Config 29 */
+#define MPFS_GPIO_CONFIG_30_OFFSET    0x0078 /* GPIO Config 30 */
+#define MPFS_GPIO_CONFIG_31_OFFSET    0x007C /* GPIO Config 31 */
+#define MPFS_GPIO_INTR_OFFSET         0x0080 /* GPIO Irq state */
+#define MPFS_GPIO_GPIN_OFFSET         0x0084 /* GPIO Input states */
+#define MPFS_GPIO_GPOUT_OFFSET        0x0088 /* GPIO Ouput states */
+#define MPFS_GPIO_CONFIG_ALL_OFFSET   0x008C /* GPIO set all configs */
+#define MPFS_GPIO_CONFIG_BYTE0_OFFSET 0x0090 /* GPIO set all configs in byte-0 */
+#define MPFS_GPIO_CONFIG_BYTE1_OFFSET 0x0094 /* GPIO set all configs in byte-1 */
+#define MPFS_GPIO_CONFIG_BYTE2_OFFSET 0x0098 /* GPIO set all configs in byte-3 */
+#define MPFS_GPIO_CONFIG_BYTE3_OFFSET 0x009C /* GPIO set all configs in byte-4 */
+#define MPFS_GPIO_CLEAR_BITS_OFFSET   0x00A0 /* GPIO Clear bits */
+#define MPFS_GPIO_SET_BITS_OFFSET     0x00A4 /* GPIO Set bits */
+
+/* Register bit field definitions *******************************************/
+
+/* CONFIG_X */
+
+#define GPIO_CONFIG_EN_OUT          (1 << 0)  /* Output enable */
+#define GPIO_CONFIG_EN_IN           (1 << 1)  /* Input enable */
+#define GPIO_CONFIG_EN_OE_BUF       (1 << 2)  /* Output buffer enable */
+#define GPIO_CONFIG_EN_INT          (1 << 3)  /* Interrupt enable */
+#define GPIO_CONFIG_INT_SHIFT       (5)       /* Bits: 5-7: Interrupt Types */
+#define GPIO_CONFIG_INT_MASK        (7)
+#  define GPIO_CONFIG_INT_HIGH      (0 << GPIO_CONFIG_INT_SHIFT)
+#  define GPIO_CONFIG_INT_LOW       (1 << GPIO_CONFIG_INT_SHIFT)
+#  define GPIO_CONFIG_INT_EDGE_POS  (2 << GPIO_CONFIG_INT_SHIFT)
+#  define GPIO_CONFIG_INT_EDGE_NEG  (3 << GPIO_CONFIG_INT_SHIFT)
+#  define GPIO_CONFIG_INT_EDGE_BOTH (4 << GPIO_CONFIG_INT_SHIFT)
+
+#endif /* __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_GPIO_H */