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arch/arm/armv[7|8]-m: implement dcache clean as barrier in write-thro…
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…ugh mode

This change fixes the issue when SAMv7 GMAC sometimes does not start packet
transmission. The issue is that EMAC_NCR_TSTART is written to EMAC_NCR register
while tx descriptor is not delivered to memory.

Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
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pkarashchenko authored and xiaoxiang781216 committed Sep 8, 2023
1 parent 15f8880 commit f39de6f
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Showing 3 changed files with 4 additions and 11 deletions.
4 changes: 2 additions & 2 deletions arch/arm/src/armv7-m/arm_cache.c
Original file line number Diff line number Diff line change
Expand Up @@ -838,10 +838,10 @@ void up_clean_dcache(uintptr_t start, uintptr_t end)
start += ssize;
}
while (start < end);
#endif /* !CONFIG_ARMV7M_DCACHE_WRITETHROUGH */

ARM_DSB();
ARM_ISB();
#endif /* !CONFIG_ARMV7M_DCACHE_WRITETHROUGH */
}
#endif /* CONFIG_ARMV7M_DCACHE */

Expand Down Expand Up @@ -915,10 +915,10 @@ void up_clean_dcache_all(void)
while (tmpways--);
}
while (sets--);
#endif /* !CONFIG_ARMV7M_DCACHE_WRITETHROUGH */

ARM_DSB();
ARM_ISB();
#endif /* !CONFIG_ARMV7M_DCACHE_WRITETHROUGH */
}
#endif /* CONFIG_ARMV7M_DCACHE */

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4 changes: 2 additions & 2 deletions arch/arm/src/armv8-m/arm_cache.c
Original file line number Diff line number Diff line change
Expand Up @@ -838,10 +838,10 @@ void up_clean_dcache(uintptr_t start, uintptr_t end)
start += ssize;
}
while (start < end);
#endif /* !CONFIG_ARMV8M_DCACHE_WRITETHROUGH */

ARM_DSB();
ARM_ISB();
#endif /* !CONFIG_ARMV8M_DCACHE_WRITETHROUGH */
}
#endif /* CONFIG_ARMV8M_DCACHE */

Expand Down Expand Up @@ -915,10 +915,10 @@ void up_clean_dcache_all(void)
while (tmpways--);
}
while (sets--);
#endif /* !CONFIG_ARMV8M_DCACHE_WRITETHROUGH */

ARM_DSB();
ARM_ISB();
#endif /* !CONFIG_ARMV8M_DCACHE_WRITETHROUGH */
}
#endif /* CONFIG_ARMV8M_DCACHE */

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7 changes: 0 additions & 7 deletions arch/arm/src/samv7/sam_emac.c
Original file line number Diff line number Diff line change
Expand Up @@ -1407,13 +1407,6 @@ static int sam_transmit(struct sam_emac_s *priv, int qid)
regval |= EMAC_NCR_TSTART;
sam_putreg(priv, SAM_EMAC_NCR_OFFSET, regval);

/* REVISIT: Sometimes TSTART is missed? In this case, the symptom is
* that the packet is not sent until the next transfer when TXSTART
* is set again.
*/

sam_putreg(priv, SAM_EMAC_NCR_OFFSET, regval);

/* Setup the TX timeout watchdog (perhaps restarting the timer) */

wd_start(&priv->txtimeout, SAM_TXTIMEOUT,
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