arch:riscv64:basic porting for C906.

arch/risc-v/Kconfig

@@ -61,6 +61,12 @@ config ARCH_CHIP_ESP32C3
 	---help---
 		Espressif ESP32-C3 (RV32IMC).
 
+config ARCH_CHIP_C906
+	bool "THEAD C906"
+	select ARCH_RV64GC
+	---help---
+		THEAD C906 processor (RISC-V 64bit core with GCVX extensions).
+
 config ARCH_CHIP_RISCV_CUSTOM
 	bool "Custom RISC-V chip"
 	select ARCH_CHIP_CUSTOM
@@ -99,6 +105,7 @@ config ARCH_CHIP
 	default "gap8"		if ARCH_CHIP_GAP8
 	default "bl602"		if ARCH_CHIP_BL602
 	default "esp32c3"	if ARCH_CHIP_ESP32C3
+	default "c906"		if ARCH_CHIP_C906
 
 config NR5_MPU
 	bool "MPU support"
@@ -137,4 +144,7 @@ endif
 if ARCH_CHIP_ESP32C3
 source arch/risc-v/src/esp32c3/Kconfig
 endif
+if ARCH_CHIP_C906
+source arch/risc-v/src/c906/Kconfig
+endif
 endif

arch/risc-v/include/c906/chip.h

@@ -0,0 +1,34 @@
+/****************************************************************************
+ * arch/risc-v/include/c906/chip.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_INCLUDE_C906_CHIP_H
+#define __ARCH_RISCV_INCLUDE_C906_CHIP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <stdint.h>
+
+#include <arch/irq.h>
+
+#endif /* __ARCH_RISCV_INCLUDE_C906_CHIP_H */

arch/risc-v/include/c906/irq.h

@@ -0,0 +1,107 @@
+/****************************************************************************
+ * arch/risc-v/include/c906/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_INCLUDE_C906_IRQ_H
+#define __ARCH_RISCV_INCLUDE_C906_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <arch/irq.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Map RISC-V exception code to NuttX IRQ */
+
+/* IRQ 0-15 : (exception:interrupt=0) */
+
+#define C906_IRQ_IAMISALIGNED  (0) /* Instruction Address Misaligned */
+#define C906_IRQ_IAFAULT       (1) /* Instruction Address Fault */
+#define C906_IRQ_IINSTRUCTION  (2) /* Illegal Instruction */
+#define C906_IRQ_BPOINT        (3) /* Break Point */
+#define C906_IRQ_LAMISALIGNED  (4) /* Load Address Misaligned */
+#define C906_IRQ_LAFAULT       (5) /* Load Access Fault */
+#define C906_IRQ_SAMISALIGNED  (6) /* Store/AMO Address Misaligned */
+#define C906_IRQ_SAFAULT       (7) /* Store/AMO Access Fault */
+#define C906_IRQ_ECALLU        (8) /* Environment Call from U-mode */
+
+#define C906_IRQ_ECALLM       (11) /* Environment Call from M-mode */
+
+/* IRQ 16- : (async event:interrupt=1) */
+
+#define C906_IRQ_ASYNC        (16)
+#define C906_IRQ_SSOFT    (C906_IRQ_ASYNC + 1)  /* Supervisor Software Int */
+#define C906_IRQ_MSOFT    (C906_IRQ_ASYNC + 3)  /* Machine Software Int */
+#define C906_IRQ_STIMER   (C906_IRQ_ASYNC + 5)  /* Supervisor Timer Int */
+#define C906_IRQ_MTIMER   (C906_IRQ_ASYNC + 7)  /* Machine Timer Int */
+#define C906_IRQ_SEXT     (C906_IRQ_ASYNC + 9)  /* Supervisor External Int */
+#define C906_IRQ_MEXT     (C906_IRQ_ASYNC + 11) /* Machine External Int */
+#define C906_IRQ_HPMOV    (C906_IRQ_ASYNC + 17) /* HPM Overflow Int */
+
+/* Machine Global External Interrupt */
+
+#define C906_IRQ_PERI_START   (C906_IRQ_ASYNC + 18)
+
+#ifdef CONFIG_C906_WITH_QEMU
+#define C906_IRQ_UART0        (C906_IRQ_PERI_START + 32)
+#else
+#define C906_IRQ_UART0        (C906_IRQ_PERI_START + 32)
+#endif
+
+/* Total number of IRQs */
+
+#define NR_IRQS               (C906_IRQ_UART0 + 1)
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+EXTERN irqstate_t  up_irq_save(void);
+EXTERN void up_irq_restore(irqstate_t);
+EXTERN irqstate_t up_irq_enable(void);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_RISCV_INCLUDE_C906_IRQ_H */

arch/risc-v/src/c906/Kconfig

@@ -0,0 +1,36 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+
+comment "C906 Configuration Options"
+
+menu "C906 Peripheral Support"
+
+# These "hidden" settings determine whether a peripheral option is available
+# for the selected MCU
+
+config C906_HAVE_UART0
+	bool
+	default y
+	select UART0_SERIALDRIVER
+	select ARCH_HAVE_SERIAL_TERMIOS
+
+# These are the peripheral selections proper
+
+config C906_UART0
+	bool "UART0"
+	default y
+	select ARCH_HAVE_UART0
+	select ARCH_HAVE_SERIAL_TERMIOS
+	select C906_UART
+
+endmenu
+
+menu "C906 Others"
+
+config C906_WITH_QEMU
+	bool "qemu support"
+	default n
+
+endmenu

arch/risc-v/src/c906/Make.defs

@@ -0,0 +1,58 @@
+############################################################################
+# arch/risc-v/src/c906/Make.defs
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements.  See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership.  The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License.  You may obtain a copy of the License at
+#
+#   http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+# Specify our HEAD assembly file.  This will be linked as
+# the first object file, so it will appear at address 0
+HEAD_ASRC = c906_vectors.S
+
+# Specify our general Assembly files
+CHIP_ASRCS = c906_head.S
+
+# Specify C code within the common directory to be included
+CMN_CSRCS  += riscv_initialize.c riscv_swint.c
+CMN_CSRCS  += riscv_allocateheap.c riscv_createstack.c riscv_exit.c riscv_fault.c
+CMN_CSRCS  += riscv_assert.c riscv_blocktask.c riscv_copystate.c riscv_initialstate.c
+CMN_CSRCS  += riscv_interruptcontext.c riscv_modifyreg32.c riscv_puts.c
+CMN_CSRCS  += riscv_releasepending.c riscv_reprioritizertr.c
+CMN_CSRCS  += riscv_releasestack.c riscv_stackframe.c riscv_schedulesigaction.c
+CMN_CSRCS  += riscv_sigdeliver.c riscv_unblocktask.c riscv_usestack.c
+CMN_CSRCS  += riscv_mdelay.c riscv_copyfullstate.c
+
+ifeq ($(CONFIG_STACK_COLORATION),y)
+CMN_CSRCS += riscv_checkstack.c
+endif
+
+ifeq ($(CONFIG_ARCH_HAVE_VFORK),y)
+CMN_CSRCS  += riscv_vfork.c
+endif
+
+# Specify our C code within this directory to be included
+CHIP_CSRCS  = c906_allocateheap.c c906_clockconfig.c
+CHIP_CSRCS += c906_idle.c c906_irq.c c906_irq_dispatch.c
+CHIP_CSRCS += c906_lowputc.c c906_serial.c
+CHIP_CSRCS += c906_start.c c906_timerisr.c
+
+ifeq ($(CONFIG_BUILD_PROTECTED),y)
+CMN_CSRCS  += riscv_task_start.c riscv_pthread_start.c
+CMN_CSRCS  += riscv_signal_dispatch.c
+CMN_UASRCS += riscv_signal_handler.S
+
+CHIP_CSRCS += c906_userspace.c
+endif

arch/risc-v/src/c906/c906.h

@@ -0,0 +1,38 @@
+/****************************************************************************
+ * arch/risc-v/src/c906/c906.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_C906_C906_H
+#define __ARCH_RISCV_SRC_C906_C906_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+#include <arch/irq.h>
+#include "riscv_internal.h"
+#include "chip.h"
+#include "c906_lowputc.h"
+
+#endif /* __ARCH_RISCV_SRC_C906_C906_H */

arch/risc-v/src/c906/c906_allocateheap.c

@@ -0,0 +1,90 @@
+/****************************************************************************
+ * arch/risc-v/src/c906/c906_allocateheap.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/kmalloc.h>
+#include <nuttx/userspace.h>
+
+#include <arch/board/board.h>
+
+#include "c906.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define SRAM1_END CONFIG_RAM_END
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_allocate_kheap
+ *
+ * Description:
+ *   For the kernel build (CONFIG_BUILD_PROTECTED=y) with both kernel- and
+ *   user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function allocates
+ *   (and protects) the kernel-space heap.
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
+void up_allocate_kheap(FAR void **heap_start, size_t *heap_size)
+{
+  /* Get the unaligned size and position of the user-space heap.
+   * This heap begins after the user-space .bss section at an offset
+   * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment).
+   */
+
+  uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend;
+  ubase          += CONFIG_MM_KERNEL_HEAPSIZE;
+
+  size_t    usize = SRAM1_END - ubase;
+
+  DEBUGASSERT(ubase < (uintptr_t)SRAM1_END);
+
+  /* TODO: Adjust that size to account for MPU alignment requirements.
+   * NOTE that there is an implicit assumption that the SRAM1_END
+   * is aligned to the MPU requirement.
+   */
+
+  ubase = SRAM1_END - usize;
+
+  /* Return the kernel heap settings (i.e., the part of the heap region
+   * that was not dedicated to the user heap).
+   */
+
+  *heap_start = (FAR void *)USERSPACE->us_bssend;
+  *heap_size  = ubase - (uintptr_t)USERSPACE->us_bssend;
+}
+#endif
+
+/****************************************************************************
+ * Name: up_addregion
+ ****************************************************************************/
+
+void up_addregion(void)
+{
+}