Add support for PolarFire SoC and icicle board

Documentation/platforms/risc-v/mpfs/boards/icicle/index.rst

@@ -0,0 +1,79 @@
+====================
+PolarFire Icicle Kit
+====================
+
+.. list-table::
+   :align: center
+
+   * - .. figure:: icicle.png
+          :align: center
+
+CPU
+---
+PolarFire SoC FPGA (MPFS250T-FCVG484EES)
+
+- SiFive E51 Monitor core (1 x RV64IMAC)
+- SiFive U54 Application cores (4 x RV64GC)
+- and Secure boot
+
+
+Memory and storage
+------------------
+- 2 GB LPDDR4 x 32
+- 1 Gb SPI flash
+- 8 GB eMMC flash & SD card slot (multiplexed)
+
+
+Programming & Debugging
+-----------------------
+Onboard JTAG connector or onboard embedded FlashPro (multiplexed)
+
+- UART via micro USB
+- 52 x test points
+
+
+Interfaces
+----------
+
+- 4 x 12.7 Gbps SERDES
+- PCIe Gen2 Rootport
+- 2 x Gigabit Ethernet
+- Micro USB 2.0 Hi-Speed OTG
+- 4 x UART (via single micro USB)
+- 2 x CAN
+- 2 x SPI
+- 2 x I²C
+
+Expansion
+---------
+- Raspberry Pi compatible 40-pin header
+- mikroBUS socket
+
+Sensor
+------
+- Power sensor (pac1934)
+
+
+
+Buttons and LEDs
+================
+
+Buttons
+-------
+There are 3 buttons and reset button.  The Reset button is not available
+to software by default.
+
+
+LEDs
+----
+There is 4 user controlled on-board LEDs.
+
+
+Configurations
+==============
+
+nsh
+---
+
+Basic configuration to run the NuttShell (nsh).
+

Documentation/platforms/risc-v/mpfs/index.rst

@@ -0,0 +1,82 @@
+===========================
+Microchip Polarfile (MPFS)
+===========================
+
+RV64 64-bit RISC-V multiprocessor-based Microcontroller Subsystem
+(MPFS025T, MPFS095T, MPFS160T, MPFS250T, MPFS460T)
+
+
+MPFS Toolchain
+==============
+
+A generic RISC-V toolchain can be used to build MPFS projects.
+Like: https://xpack.github.io/riscv-none-embed-gcc or https://github.com/sifive/freedom-tools/releases
+
+
+Booting
+=======
+
+The NuttX port for now relies on HSS bootloader to carry on some hardware initializations.
+
+
+Building and flashing
+=====================
+
+First make sure that ``hss-payload-generator`` is installed.
+Available from: https://github.com/polarfire-soc/hart-software-services
+
+This tool is used to convert the ELF/bin to a compatible HSS payload image
+
+Configure the NuttX project: ``./tools/configure.sh icicle:nsh``
+Run ``make`` to build the project.
+
+Create HSS payload bin::
+
+  hss-payload-generator -v -c hss-nuttx.yml payload.bin
+
+
+Debugging with OpenOCD
+======================
+
+Compatible OpenOCD and configs can be downloaded from:
+https://www.microsemi.com/product-directory/design-tools/4879-softconsole#downloads
+
+
+OpenOCD can then be used::
+
+   openocd -c "set DEVICE MPFS" --file board/microsemi-riscv.cfg
+
+
+Peripheral Support
+==================
+
+The following list indicates the state of peripherals' support in NuttX:
+
+============   =======  =====
+Peripheral     Support  NOTES
+============   =======  =====
+GPIO           Yes      
+MMUART         Yes      Uart mode only
+SPI            No       
+I2C            No       
+Timers         No       
+Watchdog       No       
+RTC            No       
+CAN            No       
+eNVM           No       
+USB            No       
+eMMC SD/SDIO   No       
+============   =======  =====
+
+
+
+Supported Boards
+================
+
+.. toctree::
+   :glob:
+   :maxdepth: 1
+
+   boards/*/*
+
+

arch/risc-v/Kconfig

@@ -60,6 +60,13 @@ config ARCH_CHIP_C906
 	---help---
 		THEAD C906 processor (RISC-V 64bit core with GCVX extensions).
 
+config ARCH_CHIP_MPFS
+        bool "MicroChip Polarfire (MPFS)"
+        select ARCH_RV64GC
+        select ARCH_HAVE_MPU
+        ---help---
+		MicroChip Polarfire processor (RISC-V 64bit core with GCVX extensions).
+
 config ARCH_CHIP_RISCV_CUSTOM
 	bool "Custom RISC-V chip"
 	select ARCH_CHIP_CUSTOM
@@ -97,6 +104,7 @@ config ARCH_CHIP
 	default "bl602"		if ARCH_CHIP_BL602
 	default "esp32c3"	if ARCH_CHIP_ESP32C3
 	default "c906"		if ARCH_CHIP_C906
+	default "mpfs"		if ARCH_CHIP_MPFS
 
 if ARCH_RV32IM
 source arch/risc-v/src/rv32im/Kconfig
@@ -122,4 +130,7 @@ endif
 if ARCH_CHIP_C906
 source arch/risc-v/src/c906/Kconfig
 endif
+if ARCH_CHIP_MPFS
+source arch/risc-v/src/mpfs/Kconfig
+endif
 endif

arch/risc-v/include/mpfs/chip.h

@@ -0,0 +1,34 @@
+/****************************************************************************
+ * arch/risc-v/include/mpfs/chip.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_INCLUDE_MPFS_CHIP_H
+#define __ARCH_RISCV_INCLUDE_MPFS_CHIP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <stdint.h>
+
+#include <arch/irq.h>
+
+#endif /* __ARCH_RISCV_INCLUDE_MPFS_CHIP_H */