Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

arm/armv7-a/r: set the default CPU mode to System #5734

Merged
merged 1 commit into from Mar 14, 2022
Merged

arm/armv7-a/r: set the default CPU mode to System #5734

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Jump to
Jump to file
Failed to load files.
Diff view
Diff view
4 changes: 2 additions & 2 deletions arch/arm/src/arm/arm_head.S
View file
Open in desktop
Expand Up @@ -220,9 +220,9 @@
.type __start, #function

__start:
/* Make sure that we are in SVC mode with all IRQs disabled */
/* Make sure that we are in SYS mode with all IRQs disabled */

mov r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
mov r0, #(PSR_MODE_SYS | PSR_I_BIT | PSR_F_BIT)
msr cpsr_c, r0

/* Initialize DRAM using a macro provided by board-specific logic */
Expand Down
4 changes: 2 additions & 2 deletions arch/arm/src/arm/arm_initialstate.c
View file
Open in desktop
Expand Up @@ -111,7 +111,7 @@ void up_initial_state(struct tcb_s *tcb)
{
/* It is a kernel thread.. set supervisor mode */

cpsr = PSR_MODE_SVC | PSR_F_BIT;
cpsr = PSR_MODE_SYS | PSR_F_BIT;
}
else
{
Expand All @@ -124,7 +124,7 @@ void up_initial_state(struct tcb_s *tcb)
* supervisor-mode.
*/

cpsr = PSR_MODE_SVC | PSR_F_BIT;
cpsr = PSR_MODE_SYS | PSR_F_BIT;
#endif

/* Enable or disable interrupts, based on user configuration */
Expand Down
2 changes: 1 addition & 1 deletion arch/arm/src/arm/arm_nommuhead.S
View file
Open in desktop
Expand Up @@ -58,7 +58,7 @@ __start:

/* First, setup initial processor mode */

mov r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT )
mov r0, #(PSR_MODE_SYS | PSR_I_BIT | PSR_F_BIT )
msr cpsr, r0

/* Setup system stack (and get the BSS range) */
Expand Down
4 changes: 2 additions & 2 deletions arch/arm/src/arm/arm_schedulesigaction.c
View file
Open in desktop
Expand Up @@ -130,7 +130,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
*/

CURRENT_REGS[REG_PC] = (uint32_t)arm_sigdeliver;
CURRENT_REGS[REG_CPSR] = PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT;
CURRENT_REGS[REG_CPSR] = PSR_MODE_SYS | PSR_I_BIT | PSR_F_BIT;

/* And make sure that the saved context in the TCB
* is the same as the interrupt return context.
Expand Down Expand Up @@ -162,7 +162,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
*/

tcb->xcp.regs[REG_PC] = (uint32_t)arm_sigdeliver;
tcb->xcp.regs[REG_CPSR] = PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT;
tcb->xcp.regs[REG_CPSR] = PSR_MODE_SYS | PSR_I_BIT | PSR_F_BIT;
}
}
}