arch: inline up_interrupt_context()

arch/arm/include/irq.h

@@ -29,6 +29,11 @@
  * Included Files
  ****************************************************************************/
 
+#include <sys/types.h>
+#ifndef __ASSEMBLY__
+#  include <stdbool.h>
+#endif
+
 /* Include NuttX-specific IRQ definitions */
 
 #include <nuttx/irq.h>
@@ -55,4 +60,91 @@
 #  include <arch/arm/irq.h>
 #endif
 
+#ifndef __ASSEMBLY__
+
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/* g_current_regs[] holds a references to the current interrupt level
+ * register storage structure.  If is non-NULL only during interrupt
+ * processing.  Access to g_current_regs[] must be through the macro
+ * CURRENT_REGS for portability.
+ */
+
+/* For the case of architectures with multiple CPUs, then there must be one
+ * such value for each processor that can receive an interrupt.
+ */
+
+EXTERN volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS];
+#define CURRENT_REGS (g_current_regs[up_cpu_index()])
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_cpu_index
+ *
+ * Description:
+ *   Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
+ *   corresponds to the currently executing CPU.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
+ *   corresponds to the currently executing CPU.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SMP
+int up_cpu_index(void);
+#else
+#  define up_cpu_index() (0)
+#endif
+
+/****************************************************************************
+ * Inline functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_interrupt_context
+ *
+ * Description:
+ *   Return true is we are currently executing in the interrupt
+ *   handler context.
+ *
+ ****************************************************************************/
+
+static inline bool up_interrupt_context(void)
+{
+#ifdef CONFIG_SMP
+  irqstate_t flags = up_irq_save();
+#endif
+
+  bool ret = CURRENT_REGS != NULL;
+
+#ifdef CONFIG_SMP
+  up_irq_restore(flags);
+#endif
+
+  return ret;
+}
+#endif /* __ASSEMBLY__ */
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+
 #endif /* __ARCH_ARM_INCLUDE_IRQ_H */

arch/arm/src/common/Make.defs

@@ -22,7 +22,7 @@
 
 CMN_CSRCS += arm_allocateheap.c arm_assert.c arm_blocktask.c
 CMN_CSRCS += arm_createstack.c arm_exit.c arm_fullcontextrestore.c
-CMN_CSRCS += arm_initialize.c arm_interruptcontext.c arm_lowputs.c
+CMN_CSRCS += arm_initialize.c arm_lowputs.c
 CMN_CSRCS += arm_modifyreg16.c arm_modifyreg32.c
 CMN_CSRCS += arm_modifyreg8.c arm_puts.c arm_releasepending.c
 CMN_CSRCS += arm_releasestack.c arm_reprioritizertr.c arm_saveusercontext.c

arch/arm/src/common/arm_internal.h

@@ -160,19 +160,6 @@ extern "C"
 #define EXTERN extern
 #endif
 
-/* g_current_regs[] holds a references to the current interrupt level
- * register storage structure.  If is non-NULL only during interrupt
- * processing.  Access to g_current_regs[] must be through the macro
- * CURRENT_REGS for portability.
- */
-
-/* For the case of architectures with multiple CPUs, then there must be one
- * such value for each processor that can receive an interrupt.
- */
-
-EXTERN volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS];
-#define CURRENT_REGS (g_current_regs[up_cpu_index()])
-
 /* This is the beginning of heap as provided from arm_head.S.
  * This is the first address in DRAM after the loaded
  * program+bss+idle stack.  The end of the heap is

arch/avr/include/irq.h

@@ -29,6 +29,11 @@
  * Included Files
  ****************************************************************************/
 
+#include <sys/types.h>
+#ifndef __ASSEMBLY__
+#  include <stdbool.h>
+#endif
+
 /* Include NuttX-specific IRQ definitions */
 
 #include <nuttx/irq.h>
@@ -55,26 +60,65 @@
  * Public Types
  ****************************************************************************/
 
-/****************************************************************************
- * Inline functions
- ****************************************************************************/
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
 
 /****************************************************************************
  * Public Data
  ****************************************************************************/
 
+#ifndef __ASSEMBLY__
+/* This holds a references to the current interrupt level register storage
+ * structure.  If is non-NULL only during interrupt processing.
+ */
+
+#ifdef CONFIG_ARCH_FAMILY_AVR32
+EXTERN volatile uint32_t *g_current_regs;
+#else
+EXTERN volatile uint8_t *g_current_regs;
+#endif
+
 /****************************************************************************
  * Public Function Prototypes
  ****************************************************************************/
 
-#ifndef __ASSEMBLY__
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C"
-{
-#else
-#define EXTERN extern
-#endif
+/****************************************************************************
+ * Name: up_cpu_index
+ *
+ * Description:
+ *   Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
+ *   corresponds to the currently executing CPU.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
+ *   corresponds to the currently executing CPU.
+ *
+ ****************************************************************************/
+
+#define up_cpu_index() (0)
+
+/****************************************************************************
+ * Inline functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_interrupt_context
+ *
+ * Description:
+ *   Return true is we are currently executing in the interrupt
+ *   handler context.
+ *
+ ****************************************************************************/
+
+#define up_interrupt_context() (g_current_regs != NULL)
 
 #undef EXTERN
 #ifdef __cplusplus

arch/avr/src/at32uc3/Make.defs

@@ -27,7 +27,7 @@ HEAD_ASRC = up_nommuhead.S
 CMN_ASRCS  = up_exceptions.S up_fullcontextrestore.S up_switchcontext.S
 CMN_CSRCS  = up_assert.c up_allocateheap.c up_blocktask.c up_copystate.c
 CMN_CSRCS += up_createstack.c up_mdelay.c up_udelay.c up_exit.c up_idle.c
-CMN_CSRCS += up_initialize.c up_initialstate.c up_interruptcontext.c
+CMN_CSRCS += up_initialize.c up_initialstate.c
 CMN_CSRCS += up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c
 CMN_CSRCS += up_releasepending.c up_releasestack.c up_reprioritizertr.c
 CMN_CSRCS += up_schedulesigaction.c up_sigdeliver.c up_stackframe.c

arch/avr/src/at90usb/Make.defs

@@ -27,7 +27,7 @@ HEAD_ASRC = at90usb_head.S
 CMN_ASRCS  = up_switchcontext.S
 CMN_CSRCS  = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c
 CMN_CSRCS += up_createstack.c up_doirq.c up_exit.c  up_idle.c up_initialize.c
-CMN_CSRCS += up_initialstate.c up_interruptcontext.c up_irq.c up_lowputs.c
+CMN_CSRCS += up_initialstate.c up_irq.c up_lowputs.c
 CMN_CSRCS += up_mdelay.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c
 CMN_CSRCS += up_puts.c up_releasepending.c up_releasestack.c
 CMN_CSRCS += up_reprioritizertr.c up_schedulesigaction.c up_sigdeliver.c

arch/avr/src/atmega/Make.defs

@@ -27,7 +27,7 @@ HEAD_ASRC = atmega_head.S
 CMN_ASRCS  = up_switchcontext.S
 CMN_CSRCS  = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c
 CMN_CSRCS += up_createstack.c up_doirq.c up_exit.c  up_idle.c up_initialize.c
-CMN_CSRCS += up_initialstate.c up_interruptcontext.c up_irq.c up_lowputs.c
+CMN_CSRCS += up_initialstate.c up_irq.c up_lowputs.c
 CMN_CSRCS += up_mdelay.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c
 CMN_CSRCS += up_puts.c up_releasepending.c up_releasestack.c
 CMN_CSRCS += up_reprioritizertr.c up_schedulesigaction.c up_sigdeliver.c

arch/avr/src/avr/avr.h

@@ -55,12 +55,6 @@
  ****************************************************************************/
 
 #ifndef __ASSEMBLY__
-/* This holds a references to the current interrupt level register storage
- * structure.  If is non-NULL only during interrupt processing.
- */
-
-extern volatile uint8_t *g_current_regs;
-
 /* This is the beginning of heap as provided from up_head.S. This is the
  * first address in DRAM after the loaded program+bss+idle stack.  The end
  * of the heap is CONFIG_RAM_END

arch/avr/src/avr32/avr32.h

@@ -65,12 +65,6 @@
  ****************************************************************************/
 
 #ifndef __ASSEMBLY__
-/* This holds a references to the current interrupt level register storage
- * structure.  If is non-NULL only during interrupt processing.
- */
-
-extern volatile uint32_t *g_current_regs;
-
 /* This is the beginning of heap as provided from up_head.S. This is the
  * first address in DRAM after the loaded program+bss+idle stack.
  * The end of the heap is CONFIG_RAM_END

arch/avr/src/common/up_internal.h

@@ -29,6 +29,8 @@
 
 #ifndef __ASSEMBLY__
 #  include <stdint.h>
+#  include <nuttx/arch.h>
+#  include <nuttx/irq.h>
 #endif
 
 #ifdef CONFIG_ARCH_FAMILY_AVR32