boards/risc-v/mpfs/m100pfsevp/include/board_liberodefs.h: Update memo… #6462
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…ry initialization parameters Sync some of the AXI configuration and DDR training parameters with the manufacturer's defaults. The TIP_CFG parameter correction helps with DDR training failures on some individual boards The AXI end address values fix early random crash in power-on boot on some individual boards Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
pkarashchenko
approved these changes
Jun 17, 2022
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…ry initialization parameters
Sync some of the AXI configuration and DDR training parameters with the manufacturer's
defaults.
The TIP_CFG parameter correction helps with DDR training failures on some individual boards
The AXI end address values fix early random crash in power-on boot on some individual boards
Signed-off-by: Jukka Laitinen jukkax@ssrc.tii.ae
Summary
Update memory initialization parameters for PolarFire SOC FPGA for Aries SOM
Impact
This fixes random boot problems on ARIES M100PFS SOM modules, when DDR memory is used
Testing
Tested by repeatedly booting on a bunch of Aries SOM modules in different temperatures using temperature chamber