arch/risc-v: Fix save/load FPU macros

[pussuw]

Summary

The macros destroy t0, t1, t2 when used, make them explicitly restore them so they are safe to use from where-ever

Impact

Make the save/load FPU macros safe to use from whichever location

Testing

icicle:nsh

[pussuw]

This patches something I found out long ago, the save/load macros use t0,t1,t2 as temp registers but do not explicitly restore them. Instead the macros assume they will be restored later (order of execution in riscv_exception_common.S)

[xiaoxiang781216]

@pussuw does your change same as #9103?

[pussuw]

@pussuw does your change same as #9103?

@xiaoxiang781216 No I don't think so. #9103 seems to be related to the floating point status register and saving / restoring the FPU registers.

My patch prevents corrupting the integer registers t0...t2 when using the fpu save/load macros, it does not change how the floating point status register or FPU registers are handled.