[TIR][Bugfix] Fix AXIS_SEPARATORS in tir.Schedule.transform_layout #13326
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Preivously, the block SREF reuse only included a single step of changes, and would have an incorrect mapping if multiple sequential changes to the TIR block occurred. This could happen if a `BufferStore` was updated, followed by replacement of `Block` iter vars/values. This commit tracks the Block replacements across each usage, to ensure the SREF instances remain valid.
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vinx13
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xinetzone
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…pache#13326) Preivously, the block SREF reuse only included a single step of changes, and would have an incorrect mapping if multiple sequential changes to the TIR block occurred. This could happen if a `BufferStore` was updated, followed by replacement of `Block` iter vars/values. This commit tracks the Block replacements across each usage, to ensure the SREF instances remain valid.
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Preivously, the block SREF reuse only included a single step of changes, and would have an incorrect mapping if multiple sequential changes to the TIR block occurred. This could happen if a
BufferStorewas updated, followed by replacement ofBlockiter vars/values. This commit tracks the Block replacements across each usage, to ensure the SREF instances remain valid.