Develop #20
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…demonstrator CM added.
- Clock inputs and LHC clock output. - Legacy TTC data. - Spare MCU connections. - Spare SM-CM connections. - Spare I2C bus. - Expansion and debug headers. - Inter-FPGA connections (KU15P - ZU11EG).
… line rate and 100 MHz reference clock.
…he FELIX IBERT is now running with 10 Gbps and 240 MHz reference clock.
…orks well with 10 Gbps line rate and 240 MHz reference clock.
…erence clock. The links of the MGT banks 133 and 134 work well with a loopback fiber connected to the FireFly 1 of the CM. The links of the MGT bank 132 don't work, because their RX ports are not connected.
…ERT added, some clock signals routed to debug header X39.
The line rates are 2.56, 4.80, and 10.24 Gbps. The reference clock speed is 320 MHz for all line rates.
Conflicts: configs/MPI_rev1_p1_KU15p-2/autogen/AddSlaves_MPI_rev1_p1_KU15p-2.tcl configs/MPI_rev1_p1_KU15p-2/files.tcl configs/MPI_rev1_p1_KU15p-2/slaves.yaml configs/MPI_rev1_p1_KU15p-2/src/top.vhd
…cking branch 'upstream/develop' into develop.
… and 9.6 Gpbs with 240 MHz reference clock.
… created as text and XML files.
…es (finally, hopefully).
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New AXI slave for control of user LEDs of the MPI CM KU15P.