init refactor

imxrt1060-hal/src/can/frame.rs

@@ -227,6 +227,64 @@ impl PartialEq for Data {
 
 impl Eq for Data {}
 
+#[derive(Debug, Copy, Clone)]
+pub struct Code {
+    // substitute remote request
+    pub(crate) srr: bool,
+    // ID extended
+    pub(crate) ide: bool,
+    // remote
+    pub(crate) rtr: bool,
+    // data length code
+    pub(crate) dlc: u8,
+    // timestamp
+    pub(crate) timestamp: u16,
+}
+
+impl Code {
+    const SRR_SHIFT: u32 = 22;
+    const SRR_MASK: u32 = 0b1_u32 << Self::SRR_SHIFT;
+
+    const IDE_SHIFT: u32 = 21;
+    const IDE_MASK: u32 = 0b1_u32 << Self::IDE_SHIFT;
+
+    const RTR_SHIFT: u32 = 20;
+    const RTR_MASK: u32 = 0b1_u32 << Self::RTR_SHIFT;
+
+    const DLC_SHIFT: u32 = 16;
+    const DLC_MASK: u32 = 0b111_u32 << Self::DLC_SHIFT;
+
+    const TIMESTAMP_SHIFT: u32 = 0;
+    const TIMESTAMP_MASK: u32 = 0xFFFF_u32 << Self::TIMESTAMP_SHIFT;
+
+    #[inline]
+    fn to_reg(&self, frame: &Frame) -> u32 {
+        self.srr() | self.ide() | self.dlc() | self.timestamp()
+    }
+
+    #[inline]
+    fn srr(&self) -> u32 {
+        if self.srr { Self::SRR_MASK } else { 0_u32 }
+    }
+
+    #[inline]
+    fn ide(&self) -> u32 {
+        if self.ide { Self::IDE_MASK } else { 0_u32 }
+    }
+
+    #[inline]
+    fn dlc(&self) -> u32 {
+        (self.dlc as u32) << Self::DLC_SHIFT
+    }
+
+    #[inline]
+    fn timestamp(&self) -> u32 {
+        (self.timestamp as u32) << Self::TIMESTAMP_SHIFT
+    }
+
+}
+
+
 #[cfg(feature = "unstable-defmt")]
 impl defmt::Format for Data {
     fn format(&self, fmt: defmt::Formatter<'_>) {

imxrt1060-hal/src/can/id.rs

@@ -15,9 +15,9 @@ use core::cmp::{Ord, Ordering};
 pub struct IdReg(u32);
 
 impl IdReg {
-    const STANDARD_SHIFT: u32 = 21;
+    const STANDARD_SHIFT: u32 = 18;
 
-    const EXTENDED_SHIFT: u32 = 3;
+    const EXTENDED_SHIFT: u32 = 1;
 
     const IDE_MASK: u32 = 0x0000_0004;
 

imxrt1060-hal/src/can/mod.rs

@@ -151,7 +151,7 @@ impl From<&MailboxData> for MailboxDataInfo {
         Self {
             remote: d.code & (1_u32 << 20) == 1,
             extended,
-            id: id,
+            id,
             length: ((d.code & 0xF0000_u32) >> 16) as u8,
             timestamp: d.code & 0xFFFF_u32,
         }
@@ -259,16 +259,6 @@ where
                 mailbox_idflt_tab_addr,
                 idflt_tab
             );
-            // if mailbox_number < constrain(self.mailbox_offset(), 0, 32) as u32 {
-            //     let mailbox_rximr_addr = self.mailbox_number_to_rximr_address(mailbox_number as u8);
-            //     let rximr = unsafe { core::ptr::read_volatile((mailbox_rximr_addr) as *mut u32) };
-            //     log::info!(
-            //         "RXIMR[{}, {:X}]: {:X}",
-            //         mailbox_number,
-            //         mailbox_rximr_addr,
-            //         rximr
-            //     );
-            // }
         }
     }
 
@@ -1074,7 +1064,36 @@ where
         self.write_mailbox(mailbox_number, Some(code), None, None, None);
     }
 
+    /// Write data to an available TX Mailbox.
+    ///
+    /// This will accept both standard and extended data and remote frames with any ID.
+    ///
+    /// In order to transmit a CAN frame, the CPU must prepare a Message Buffer for
+    /// transmission by executing the procedure found here.
+    /// 
+    /// 1. Check if the respective interruption bit is set and clear it.
+    /// 
+    /// 2. If the MB is active (transmission pending), write the ABORT code (0b1001) to the
+    /// CODE field of the Control and Status word to request an abortion of the
+    /// transmission. Wait for the corresponding IFLAG to be asserted by polling the IFLAG
+    /// register or by the interrupt request if enabled by the respective IMASK. Then read
+    /// back the CODE field to check if the transmission was aborted or transmitted (see
+    /// Transmission Abort Mechanism). If backwards compatibility is desired (MCR[AEN]
+    /// bit negated), just write the INACTIVE code (0b1000) to the CODE field to inactivate
+    /// the MB but then the pending frame may be transmitted without notification (see
+    /// Message Buffer Inactivation).
+    /// 
+    /// 3. Write the ID word.
+    /// 
+    /// 4. Write the data bytes.
+    /// 
+    /// 5. Write the DLC, Control and Code fields of the Control and Status word to activate
+    /// the MB.
+    /// 
+    /// Once the MB is activated, it will participate into the arbitration process and eventually be
+    /// transmitted according to its priority.
     fn write_tx_mailbox_2(&mut self, mailbox_number: u8, id: u32, data: [u8; 8]) {
+        // Check if the respective interruption bit is set and clear it.
         self.write_iflag_bit(mailbox_number);
         let mut code: u32 = 0x00;
         self.write_mailbox(