3rd time's a charm, fix CI issues

imxrt-hal/src/adc.rs

@@ -1,41 +1,42 @@
 //! ADC
-//! 
+//!
 //! This ADC driver supports `embedded_hal`'s ADC traits
-//! 
+//!
 //! # Example
 //! ```no_run
 //! use imxrt_hal::{self, adc};
+//! use embedded_hal::adc::OneShot;
 //!
 //! let mut peripherals = imxrt_hal::Peripherals::take().unwrap();
 //! let (adc1_builder, _) = peripherals.adc.clock(&mut peripherals.ccm.handle);
-//! 
+//!
 //! let mut adc1 = adc1_builder.build(adc::ClockSelect::default(), adc::ClockDivision::default());
 //! let mut a1 = adc::AnalogInput::new(peripherals.iomuxc.ad_b1.p02, &adc1);
-//! 
+//!
 //! let reading: u16 = adc1.read(&mut a1).unwrap();
 //!```
 
 use crate::ccm;
+use crate::iomuxc::adc::{prepare_adc_pin, Pin, ADC1, ADC2};
+use crate::iomuxc::{adc, consts::Unsigned};
 use crate::ral;
-use crate::iomuxc::adc::{ADC1, ADC2, Pin, prepare_adc_pin};
-use crate::iomuxc::{consts::Unsigned, adc};
 use core::marker::PhantomData;
 use embedded_hal::adc::{Channel, OneShot};
 
 /// The clock input for an ADC
 #[allow(non_camel_case_types)]
 pub enum ClockSelect {
-    IPG,            // IPG clock
-    IPG_2,          // IPG clock / 2
-    ADACK           // Asynchronous clock 
+    IPG,   // IPG clock
+    IPG_2, // IPG clock / 2
+    ADACK, // Asynchronous clock
 }
 
 /// How much to divide the clock input
 pub enum ClockDivision {
-    Div1,           // Input clock / 1
-    Div2,           // Input clock / 2
-    Div4,           // Input clock / 4
-    Div8            // Input clock / 8
+    Div1, // Input clock / 1
+    Div2, // Input clock / 2
+    Div4, // Input clock / 4
+    Div8, // Input clock / 8
 }
 
 impl ClockSelect {
@@ -52,10 +53,10 @@ impl ClockDivision {
 
 /// Conversion speeds done by clock cycles
 pub enum ConversionSpeed {
-    Slow,       // 25 ADC clock cycles (24 on imxrt102x)
-    Medium,     // 17 ADC clock cycles (16 on imxrt102x)
-    Fast,       // 9 ADC clock cycles (8 on imxrt102x)
-    VeryFast    // 3 ADC clock cycles (2 on imxrt102x)
+    Slow,     // 25 ADC clock cycles (24 on imxrt102x)
+    Medium,   // 17 ADC clock cycles (16 on imxrt102x)
+    Fast,     // 9 ADC clock cycles (8 on imxrt102x)
+    VeryFast, // 3 ADC clock cycles (2 on imxrt102x)
 }
 
 /// Denotes how much hardware averaging to do
@@ -64,27 +65,26 @@ pub enum AveragingCount {
     Avg4,
     Avg8,
     Avg16,
-    Avg32
+    Avg32,
 }
 
 // Specifies the resolution the ADC
 pub enum ResolutionBits {
     Res8,
     Res10,
-    Res12
+    Res12,
 }
 
 /// A pin representing an analog input for a particular ADC
-pub struct AnalogInput<ADCx, P>
-{
+pub struct AnalogInput<ADCx, P> {
     _module: PhantomData<ADCx>,
-    _pin: P
+    _pin: P,
 }
 
 impl<P, ADCx> Channel<ADCx> for AnalogInput<ADCx, P>
-where 
+where
     P: Pin<ADCx>,
-    ADCx: adc::ADC
+    ADCx: adc::ADC,
 {
     type ID = u16;
 
@@ -96,28 +96,28 @@ where
 impl<P, ADCx> AnalogInput<ADCx, P>
 where
     P: Pin<ADCx>,
-    ADCx: adc::ADC
+    ADCx: adc::ADC,
 {
     /// Creates a new analog input pin
     pub fn new(mut pin: P, _adc: &ADC<ADCx>) -> Self {
         prepare_adc_pin(&mut pin);
         Self {
             _module: PhantomData,
-            _pin: pin
+            _pin: pin,
         }
     }
 }
 
 pub struct ADC<ADCx> {
     _module: PhantomData<ADCx>,
-    reg: ral::adc::Instance
+    reg: ral::adc::Instance,
 }
 
 impl<ADCx> ADC<ADCx> {
     fn new(reg: ral::adc::Instance) -> Self {
         let inst = Self {
             _module: PhantomData,
-            reg
+            reg,
         };
 
         inst.set_resolution(ResolutionBits::Res10);
@@ -143,7 +143,7 @@ impl<ADCx> ADC<ADCx> {
             ResolutionBits::Res12 => MODE_2
         });
     }
-    
+
     /// Sets the number of hardware averages taken by the ADC
     pub fn set_averaging(&self, avg: AveragingCount) {
         ral::modify_reg!(ral::adc, self.reg, GC, AVGE: match avg {
@@ -160,13 +160,13 @@ impl<ADCx> ADC<ADCx> {
 
     /// Sets the conversion speed for this ADC, see ConversionSpeed for clock cycle counts.
     pub fn set_conversion_speed(&self, conversion_speed: ConversionSpeed) {
-        ral::modify_reg!(ral::adc, self.reg, CFG, 
+        ral::modify_reg!(ral::adc, self.reg, CFG,
             ADSTS: match conversion_speed {
                 ConversionSpeed::Slow => ADSTS_3,
                 ConversionSpeed::Medium => ADSTS_1,
                 ConversionSpeed::Fast => ADSTS_3,
                 ConversionSpeed::VeryFast => ADSTS_0
-            }, 
+            },
             ADLSMP: match conversion_speed {
                 ConversionSpeed::Slow => ADLSMP_1,
                 ConversionSpeed::Medium => ADLSMP_1,
@@ -194,7 +194,7 @@ impl<ADCx, WORD, P> OneShot<ADCx, WORD, AnalogInput<ADCx, P>> for ADC<ADCx>
 where
     ADCx: adc::ADC,
     WORD: From<u16>,
-    P: Pin<ADCx>
+    P: Pin<ADCx>,
 {
     type Error = ();
 
@@ -211,11 +211,11 @@ where
 /// Unclocked ADC modules
 ///
 /// The `Unclocked` struct represents both unconfigured ADC peripherals.
-/// Once clocked, you'll have the ability to either the ADC1 or ADC2 
+/// Once clocked, you'll have the ability to use either the ADC1 or ADC2
 /// peripherals.
 pub struct Unclocked {
     pub(crate) adc1: ral::adc::Instance,
-    pub(crate) adc2: ral::adc::Instance
+    pub(crate) adc2: ral::adc::Instance,
 }
 
 impl Unclocked {
@@ -224,27 +224,24 @@ impl Unclocked {
         ral::modify_reg!(ral::ccm, ccm, CCGR1, CG8: 0b11); // adc1_clk_enable
         ral::modify_reg!(ral::ccm, ccm, CCGR1, CG4: 0b11); // adc2_clk_enable
 
-        (
-            Builder::new(self.adc1),
-            Builder::new(self.adc2)
-        )
+        (Builder::new(self.adc1), Builder::new(self.adc2))
     }
 }
 
 /// An ADC builder than can build an ADC1 or ADC2 module
 pub struct Builder<ADCx> {
     _module: PhantomData<ADCx>,
-    reg: ral::adc::Instance
+    reg: ral::adc::Instance,
 }
 
 impl<ADCx> Builder<ADCx>
-where 
-    ADCx: adc::ADC
+where
+    ADCx: adc::ADC,
 {
     fn new(reg: ral::adc::Instance) -> Self {
         Self {
             _module: PhantomData,
-            reg
+            reg,
         }
     }
 
@@ -258,7 +255,7 @@ where
         });
 
         // Select the clock selection, division, and enable ADHSC if applicable
-        ral::modify_reg!(ral::adc, self.reg, CFG, 
+        ral::modify_reg!(ral::adc, self.reg, CFG,
             ADICLK: match clock {
                 ClockSelect::IPG => ADICLK_0,
                 ClockSelect::IPG_2 => ADICLK_1,

imxrt-hal/src/lib.rs

@@ -79,7 +79,7 @@ impl Peripherals {
         Peripherals {
             adc: adc::Unclocked {
                 adc1: ral::adc::ADC1::steal(),
-                adc2: ral::adc::ADC2::steal()
+                adc2: ral::adc::ADC2::steal(),
             },
             iomuxc: iomuxc::pads(ral::iomuxc::IOMUXC::steal()),
             ccm: ccm::CCM::new(ral::ccm::CCM::steal(), ral::ccm_analog::CCM_ANALOG::steal()),
@@ -126,7 +126,7 @@ impl Peripherals {
         let p = Peripherals {
             adc: adc::Unclocked {
                 adc1: ral::adc::ADC1::take()?,
-                adc2: ral::adc::ADC2::take()?
+                adc2: ral::adc::ADC2::take()?,
             },
             iomuxc: iomuxc::pads(ral::iomuxc::IOMUXC::take()?),
             ccm: ccm::CCM::new(ral::ccm::CCM::take()?, ral::ccm_analog::CCM_ANALOG::take()?),