Set USB SRAM QoS to sensitive latency

[sameer]

By default this is 00 for both DQOS and CQOS, which means that USB is treated as a background operation and there is at least a one clock-cycle SRAM access latency. This reduces the SRAM clock-cycle latency for USB by setting it to 10, giving it higher memory access priority.

This is done by Adafruit and by the Rust SAMD21 support crate (albeit at critical sensitivity) to improve USB performance and ensure correct behavior.
Relevant datasheet section for QOSCTRL
Relevant datasheet explanation for QoS

[facchinm]

LGTM! Merging, thanks!