Revert "32x: more timing tweaks; still not truely accurate but better…

… approximates sdram timing"

This reverts commit 40a4616.

ares/component/processor/sh2/sh7604/cache.cpp

@@ -30,6 +30,7 @@ auto SH2::Cache::read(u32 address) -> u32 {
   lines[index].longs[1] = bswap32(self->busReadLong(address & 0x1fff'fff0 | 0x4));
   lines[index].longs[2] = bswap32(self->busReadLong(address & 0x1fff'fff0 | 0x8));
   lines[index].longs[3] = bswap32(self->busReadLong(address & 0x1fff'fff0 | 0xc));
+  self->step(12);
   return read(lines[index]);
 }
 

ares/md/m32x/bus-internal.cpp

@@ -27,7 +27,6 @@ auto M32X::readInternal(n1 upper, n1 lower, n32 address, n16 data) -> n16 {
   }
 
   if(address >= 0x0600'0000 && address <= 0x0603'ffff) {
-    if(shm.active()) shm.step(2); if(shs.active()) shs.step(2);
     return sdram[address >> 1 & 0x1ffff];
   }
 
@@ -66,7 +65,6 @@ auto M32X::writeInternal(n1 upper, n1 lower, n32 address, n16 data) -> void {
   }
 
   if(address >= 0x0600'0000 && address <= 0x0603'ffff) {
-    if(shm.active()) shm.step(1); if(shs.active()) shs.step(1);
     if(upper) sdram[address >> 1 & 0x1ffff].byte(1) = data.byte(1);
     if(lower) sdram[address >> 1 & 0x1ffff].byte(0) = data.byte(0);
     return;

ares/md/m32x/sh7604.cpp

@@ -73,7 +73,7 @@ auto M32X::SH7604::step(u32 clocks) -> void {
 auto M32X::SH7604::power(bool reset) -> void {
   Thread::create(23'000'000, {&M32X::SH7604::main, this});
   SH2::recompilerStepCycles =  20; // Minimum cycles for recompiler to run for each batch of instructions
-  minCyclesBetweenFullSyncs = 100; // Minimum cycles between full sync with the M68K/MD side
+  minCyclesBetweenFullSyncs = 200; // Minimum cycles between full sync with the M68K/MD side
   minCyclesBetweenSh2Syncs  =   5; // Minimum Cycles between sync with the other SH2 (syncOtherSh2)
   minCyclesBetweenM68kSyncs =  10; // Minimum Cycles between sync with the M68K (syncM68k)
   SH2::power(reset);