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watchdog: implement linecard watchdog
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Change-Id: I7d6a4b098492af443b73d0af98ac396907bd4df6
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Staphylo committed Nov 14, 2022
1 parent abfd43d commit 3a5e3c7
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Showing 4 changed files with 9 additions and 10 deletions.
9 changes: 5 additions & 4 deletions arista/drivers/scd/watchdog.py
Original file line number Diff line number Diff line change
Expand Up @@ -64,21 +64,22 @@ def remaining(self):
return self.lastTimeout - elapsed

class ScdWatchdog(Watchdog):

MAX_TIMEOUT = 65535

def __init__(self, scd, reg=0x0120):
def __init__(self, scd, reg=0x0120, action=2):
self.scd = scd
self.reg = reg
self.action = action
self.state = WatchdogState(localStorage=Config().watchdog_state_file)

@staticmethod
def armReg(timeout):
def armReg(self, timeout):
regValue = 0
if timeout > 0:
# Set enable bit
regValue |= 1 << 31
# Powercycle
regValue |= 2 << 29
regValue |= self.action << 29
# Timeout value
regValue |= timeout
return regValue
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6 changes: 2 additions & 4 deletions arista/platforms/cpu/hedgehog.py
Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,6 @@
from ...components.dpm.adm1266 import Adm1266, AdmPin
from ...components.rpc import LinecardRpcClient
from ...components.scd import Scd
from ...components.watchdog import FakeWatchdog

from ...descs.led import LedDesc, LedColor
from ...descs.sensor import SensorDesc, Position
Expand Down Expand Up @@ -44,14 +43,13 @@ def __init__(self, **kwargs):
position=Position.OTHER, target=60, overheat=90, critical=95),
])

self.inventory.addWatchdog(FakeWatchdog())

self.rpc = self.newComponent(LinecardRpcClient)
self.rpc.addLed(
LedDesc('status', colors=[LedColor.RED, LedColor.GREEN, LedColor.OFF]))
self.rpc.addPowerCycle(None)

def addSmbusComponents(self, scd):
def addScdComponents(self, scd):
scd.createWatchdog(intr=scd.getInterrupt(0), bit=10)
scd.newComponent(SbTsi, addr=scd.i2cAddr(9, 0x4c), sensors=[
SensorDesc(diode=0, name='Cpu SBTSI',
position=Position.OTHER, target=60, overheat=90, critical=95),
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2 changes: 1 addition & 1 deletion arista/platforms/linecard/clearwater.py
Original file line number Diff line number Diff line change
Expand Up @@ -83,7 +83,7 @@ def cwMainDomainCommon(self):
# mode.
if self.cpu:
self.createPorts()
self.cpu.addSmbusComponents(self.scd)
self.cpu.addScdComponents(self.scd)

def mainDomain(self):
self.cwMainDomainCommon()
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2 changes: 1 addition & 1 deletion arista/platforms/linecard/wolverine.py
Original file line number Diff line number Diff line change
Expand Up @@ -80,7 +80,7 @@ def mainDomain(self):
# mode.
if self.cpu:
self.createPorts()
self.cpu.addSmbusComponents(self.scd)
self.cpu.addScdComponents(self.scd)

def controlDomain(self):
super(Wolverine, self).controlDomain()
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