The doc folder contains the 
   Design document
The cprog folder contains the
    LZW C program
    input test files in1.txt, in2.txt, in3.txt
    LZW encoded files in1out.lzw, in2out.lzw, in3out.lzw
 The fpga_test_files folder contains the files which are downloaded into the
 FPGA for compressing
    input test files in1.txt, in2.txt, in3.txt

The models folder contains the serial port model used in simulation

The rtl folder contains the LZW rtl files

The run folder contains the "run.do" file to run the simulations in Modelsim

The tb folder contains the testbench for simulation

The test_cases contains the test files used for RTL simulations

The synth folder contains the UCF file for FPGA implementation