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Random cleanups. Kernel runs on qemu port now.

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commit 8c998fe493d6bf733a0f4d0c3c1920ac6b8fb392 1 parent 8dc9c22
@atgreen authored
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2  BUILDNUM
@@ -1 +1 @@
-84
+85
View
4 ChangeLog
@@ -1,3 +1,7 @@
+2009-09-10 Anthony Green <green@moxielogic.com>
+
+ * build.xml: Fix initramfs reference before building kernel.
+
2009-08-02 Anthony Green <green@moxielogic.com>
* dtc/*: New files.
View
14 TODO
@@ -92,3 +92,17 @@ foo:
this common operation. Maybe cmp1 might even make sense. This is easy
to measure.
+-------------------------------------------------------------------------------
+* uClinux Port
+-------------------------------------------------------------------------------
+
+ - Design early boot / handoff from firmware. Here are some initial thoughts..
+
+ - The kernel should assume that pointer to a flattened device tree is in one of
+ the special registers. How would it get there?
+
+ 1) gdb sim.. import a dts/dtb file into the sim and force it into the end or RAM,
+ then load a pointer to it into one of the special regsters.
+
+ 2) qemu.. similarly, but we should load the dtb from a file (as a .o maybe?) whose
+ name is based on the board/SoC we're simulation (moxiesim, for instance)
View
16 build.xml
@@ -328,7 +328,7 @@
<arg value="-c"/>
<arg value="(cd linux-2.6; cp arch/moxie/configs/nommu_defconfig arch/moxie/defconfig)"/>
</exec>
- <replace file="${basedir}/linux-2.6/arch/moxie/defconfig" token="@ROOTFS@" value="${basedir}/initfs/uclinux/root/" />
+ <replace file="${basedir}/linux-2.6/arch/moxie/defconfig" token="@ROOTFS@" value="${basedir}/initfs/uclinux/initramfs.txt" />
<exec executable="make">
<env key="PATH" path="${basedir}/root/usr/bin:${env.PATH}"/>
<arg value="--directory=linux-2.6"/>
@@ -438,9 +438,23 @@
</exec>
<echo message="===================================================================="/>
+ <echo message="====== Building BusyBox ============================================"/>
+ <echo message="===================================================================="/>
+ <mkdir dir="build/elf2flt"/>
+ <exec executable="make">
+ <env key="PATH" path="${basedir}/root/usr/bin:${env.PATH}"/>
+ <arg value="--directory=busybox"/>
+ </exec>
+
+ <echo message="===================================================================="/>
<echo message="====== Building initfs for uClinux ================================="/>
<echo message="===================================================================="/>
<mkdir dir="build/gcc-uclinux"/>
+ <exec executable="sh">
+ <arg value="-c"/>
+ <arg value="(cd initfs/uclinux; cp initramfs.txt.in initramfs.txt"/>
+ </exec>
+ <replace file="${basedir}/initfs/uclinux/initramfs.txt" token="@TOP@" value="${basedir}" />
<exec executable="make">
<env key="PATH" path="${basedir}/root/usr/bin:${env.PATH}"/>
<arg value="--directory=initfs/uclinux/src"/>
View
22 linux-2.6/arch/moxie/kernel/early_printk.c
@@ -28,17 +28,17 @@ static u32 base_addr;
static void early_libgloss_printk_write(struct console *unused,
const char *s, unsigned n)
{
- /* First, try the simulator escape... */
- asm ("ldi.l $r0, 0x0");
- asm ("swi 5");
-
- /* Then try writing to the qemu serial port... */
- {
- int i = 0;
- while (i < n)
- *(char *)0x3f8 = s[i++];
- return n;
- }
+ /* First, try the simulator escape... */
+ asm ("ldi.l $r0, 0x0");
+ asm ("swi 5");
+
+ /* Then try writing to the qemu serial port... */
+ {
+ int i = 0;
+ while (i < n)
+ *(char *)0x3f8 = s[i++];
+ return n;
+ }
}
extern struct tty_driver *hp_simserial_driver;
View
2  linux-2.6/arch/moxie/kernel/vmlinux.lds
@@ -1,7 +1,7 @@
/*
* Automatically generated C config: don't edit
* Linux kernel version: 2.6.31-rc3
- * Wed Aug 19 11:34:27 2009
+ * Wed Sep 9 17:34:29 2009
*/
/*
* Copyright (C) 2009 Anthony Green <green@moxielogic.com>
View
0  moxie/rtl/verilog/.vcd
No changes.
View
371 moxie/rtl/verilog/cpu_idecode.v
@@ -0,0 +1,371 @@
+// cpu_idecode.v - The instruction decode unit.
+//
+// Copyright (c) 2009 Anthony Green. All Rights Reserved.
+// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
+//
+// The above named program is free software; you can redistribute it
+// and/or modify it under the terms of the GNU General Public License
+// version 2 as published by the Free Software Foundation.
+//
+// The above named program is distributed in the hope that it will be
+// useful, but WITHOUT ANY WARRANTY; without even the implied warranty
+// of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this work; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+// 02110-1301, USA.
+
+module cpu_idecode (/*AUTOARG*/
+ // Outputs
+ idif_used_insn_o, idif_used_data_o,
+ // Inputs
+ rst_i, clk_i, ifid_insn_i, ifid_insn_data_i, ifid_insn_valid_i,
+ ifid_insn_data_valid_i
+ );
+
+ // --- Clock and Reset ------------------------------------------
+ input rst_i, clk_i;
+
+ // --- Output to Instruction Fetcher ----------------------------
+ reg used_insn, used_data;
+ output idif_used_insn_o, idif_used_data_o;
+ assign idif_used_insn_o = used_insn;
+ assign idif_used_data_o = used_data;
+
+ // --- Instruction Buffer ---------------------------------------
+ input [15:0] ifid_insn_i;
+ input [31:0] ifid_insn_data_i;
+ input ifid_insn_valid_i, ifid_insn_data_valid_i;
+ wire [15:0] ifid_insn_i;
+ wire [31:0] ifid_insn_data_i;
+ wire [0:0] ifid_insn_valid_i;
+ wire [0:0] ifid_insn_data_valid_i;
+
+ // --- Reset Logic ----------------------------------------------
+ always @ (posedge clk_i) begin
+ if (rst_i == 1) begin
+ used_insn <= 0;
+ used_data <= 0;
+ end
+ end
+
+ function [3*8:0] get_regname;
+ input [4:0] regnum;
+ case (regnum)
+ 4'b0000:
+ get_regname = "fp ";
+ 4'b0001:
+ get_regname = "sp ";
+ 4'b0010:
+ get_regname = "r0 ";
+ 4'b0011:
+ get_regname = "r1 ";
+ 4'b0100:
+ get_regname = "r2 ";
+ 4'b0101:
+ get_regname = "r3 ";
+ 4'b0110:
+ get_regname = "r4 ";
+ 4'b0111:
+ get_regname = "r5 ";
+ 4'b1000:
+ get_regname = "r6 ";
+ 4'b1001:
+ get_regname = "r7 ";
+ 4'b1010:
+ get_regname = "r8 ";
+ 4'b1011:
+ get_regname = "r9 ";
+ 4'b1100:
+ get_regname = "r10";
+ 4'b1101:
+ get_regname = "r11";
+ 4'b1110:
+ get_regname = "r12";
+ 4'b1111:
+ get_regname = "r13";
+ endcase // case (regnum)
+ endfunction
+
+ always @ (posedge clk_i) begin
+ $display("**** ifid_insn_valid_i = %d\t0x%x", ifid_insn_valid_i, ifid_insn_i);
+ $display("**** ifid_insn_data_valid_i = %d\t0x%x", ifid_insn_data_valid_i, ifid_insn_data_i);
+ if (rst_i == 0 && ifid_insn_valid_i == 1)
+ begin
+ casex (ifid_insn_i)
+ 16'b00000000????????:
+ begin
+ used_insn <= 1;
+ $display ("\tnop");
+ end
+ 16'b00000001????????:
+ if (ifid_insn_data_valid_i == 1)
+ begin
+ used_insn <= 1;
+ used_data <= 1;
+ $display ("\tldi.l\t$%0s,\t0x%x",
+ get_regname(ifid_insn_i[7:4]),
+ ifid_insn_data_i);
+ end
+ 16'b00000010????????:
+ begin
+ used_insn <= 1;
+ $display ("\tmov\t$%0s,\t%0s",
+ get_regname(ifid_insn_i[7:4]),
+ get_regname(ifid_insn_i[3:0]));
+ end
+ 16'b00000011????????:
+ if (ifid_insn_data_valid_i == 1)
+ begin
+ used_insn <= 1;
+ used_data <= 1;
+ $display ("\tjsra\t0x%x", ifid_insn_data_i);
+ end
+ 16'b00000100????????:
+ begin
+ used_insn <= 1;
+ $display ("\tret");
+ end
+ 16'b00000101????????:
+ $display ("\tadd.l\t$%0s,\t%0s",
+ get_regname(ifid_insn_i[7:4]),
+ get_regname(ifid_insn_i[3:0]));
+ 16'b00000110????????:
+ $display ("\tpush\t$%0s,\t%0s",
+ get_regname(ifid_insn_i[7:4]),
+ get_regname(ifid_insn_i[3:0]));
+ 16'b00000111????????:
+ $display ("\tpop\t$%0s,\t%0s",
+ get_regname(ifid_insn_i[7:4]),
+ get_regname(ifid_insn_i[3:0]));
+ 16'b00001000????????:
+ begin
+ $display ("\tlda.l\t0x%x", ifid_insn_data_i);
+ end
+ 16'b00001001????????:
+ begin
+ $display ("\tsta.l\t0x%x", ifid_insn_data_i);
+ end
+ 16'b00001010????????:
+ $display ("\tld.l\t$%0s,\t($%0s)",
+ get_regname(ifid_insn_i[7:4]),
+ get_regname(ifid_insn_i[3:0]));
+ 16'b00001011????????:
+ $display ("\tst.l");
+ 16'b00001100????????:
+ begin
+ $display ("\tldo.l\t0x%x", ifid_insn_data_i);
+ end
+ 16'b00001101????????:
+ begin
+ $display ("\tsto.l\t0x%x", ifid_insn_data_i);
+ end
+ 16'b00001110????????:
+ $display ("\tcmp\t$%0s,\t%0s",
+ get_regname(ifid_insn_i[7:4]),
+ get_regname(ifid_insn_i[3:0]));
+ 16'b00001111????????:
+ $display ("\tbad");
+ 16'b00010000????????:
+ $display ("\tbad");
+ 16'b00010001????????:
+ $display ("\tbad");
+ 16'b00010010????????:
+ $display ("\tbad");
+ 16'b00010011????????:
+ $display ("\tbad");
+ 16'b00010100????????:
+ $display ("\tbad");
+ 16'b00010101????????:
+ $display ("\tbad");
+ 16'b00010110????????:
+ $display ("\tbad");
+ 16'b00010111????????:
+ $display ("\tbad");
+ 16'b00011000????????:
+ $display ("\tbad");
+ 16'b00011001????????:
+ $display ("\tjsr\t$%0s",
+ get_regname(ifid_insn_i[7:4]));
+ 16'b00011010????????:
+ begin
+ $display ("\tjmpa\t0x%x", ifid_insn_data_i);
+ end
+ 16'b00011011????????:
+ begin
+ $display ("\tldi.b\t0x%x", ifid_insn_data_i);
+ end
+ 16'b00011100????????:
+ $display ("\tld.b");
+ 16'b00011101????????:
+ begin
+ $display ("\tlda.b\t0x%x", ifid_insn_data_i);
+ end
+ 16'b00011110????????:
+ $display ("\tst.b");
+ 16'b00011111????????:
+ begin
+ $display ("\tsta.b\t0x%x", ifid_insn_data_i);
+ end
+ 16'b00100000????????:
+ begin
+ $display ("\tldi.s\t0x%x", ifid_insn_data_i);
+ end
+ 16'b00100001????????:
+ $display ("\tld.s");
+ 16'b00100010????????:
+ begin
+ $display ("\tlda.s\t0x%x", ifid_insn_data_i);
+ end
+ 16'b00100011????????:
+ $display ("\tst.s");
+ 16'b00100100????????:
+ begin
+ $display ("\tsta.s\t0x%x", ifid_insn_data_i);
+ end
+ 16'b00100101????????:
+ $display ("\tjmp");
+ 16'b00100110????????:
+ $display ("\tand\t$%0s,\t%0s",
+ get_regname(ifid_insn_i[7:4]),
+ get_regname(ifid_insn_i[3:0]));
+ 16'b00100111????????:
+ begin
+ $display ("\tlshr\t$%0s,\t%0s",
+ get_regname(ifid_insn_i[7:4]),
+ get_regname(ifid_insn_i[3:0]));
+ end
+ 16'b00101000????????:
+ begin
+ $display ("\tashl\t$%0s,\t%0s",
+ get_regname(ifid_insn_i[7:4]),
+ get_regname(ifid_insn_i[3:0]));
+ end
+ 16'b00101001????????:
+ $display ("\tsub.l\t$%0s,\t%0s",
+ get_regname(ifid_insn_i[7:4]),
+ get_regname(ifid_insn_i[3:0]));
+ 16'b00101010????????:
+ $display ("\tneg");
+ 16'b00101011????????:
+ $display ("\tor\t$%0s,\t%0s",
+ get_regname(ifid_insn_i[7:4]),
+ get_regname(ifid_insn_i[3:0]));
+ 16'b00101100????????:
+ $display ("\tnot");
+ 16'b00101101????????:
+ begin
+ $display ("\tashr\t$%0s,\t%0s",
+ get_regname(ifid_insn_i[7:4]),
+ get_regname(ifid_insn_i[3:0]));
+ end
+ 16'b00101110????????:
+ $display ("\txor\t$%0s,\t%0s",
+ get_regname(ifid_insn_i[7:4]),
+ get_regname(ifid_insn_i[3:0]));
+ 16'b00101111????????:
+ $display ("\tmul.l\t$%0s,\t%0s",
+ get_regname(ifid_insn_i[7:4]),
+ get_regname(ifid_insn_i[3:0]));
+ 16'b00110000????????:
+ begin
+ $display ("\tswi\t0x%x", ifid_insn_data_i);
+ end
+ 16'b00110001????????:
+ $display ("\tdiv.l\t$%0s,\t%0s",
+ get_regname(ifid_insn_i[7:4]),
+ get_regname(ifid_insn_i[3:0]));
+ 16'b00110010????????:
+ $display ("\tudiv.l\t$%0s,\t%0s",
+ get_regname(ifid_insn_i[7:4]),
+ get_regname(ifid_insn_i[3:0]));
+ 16'b00110011????????:
+ $display ("\tmod.l\t$%0s,\t%0s",
+ get_regname(ifid_insn_i[7:4]),
+ get_regname(ifid_insn_i[3:0]));
+ 16'b00110100????????:
+ $display ("\tumod.l\t$%0s,\t%0s",
+ get_regname(ifid_insn_i[7:4]),
+ get_regname(ifid_insn_i[3:0]));
+ 16'b00110101????????:
+ $display ("\tbrk");
+ 16'b00110110????????:
+ begin
+ $display ("\tldo.b\t0x%x", ifid_insn_data_i);
+ end
+ 16'b00110111????????:
+ begin
+ $display ("\tsto.b\t0x%x", ifid_insn_data_i);
+ end
+ 16'b00111000????????:
+ begin
+ $display ("\tldo.s\t0x%x", ifid_insn_data_i);
+ end
+ 16'b00111001????????:
+ begin
+ $display ("\tsto.s\t0x%x", ifid_insn_data_i);
+ end
+ 16'b00111010????????:
+ $display ("\tbad");
+ 16'b00111011????????:
+ $display ("\tbad");
+ 16'b00111100????????:
+ $display ("\tbad");
+ 16'b00111101????????:
+ $display ("\tbad");
+ 16'b00111110????????:
+ $display ("\tbad");
+ 16'b00111111????????:
+ $display ("\tbad");
+ 16'b1000????????????:
+ $display ("\tinc\t$%0s,\t%d",
+ get_regname(ifid_insn_i[11:8]),
+ ifid_insn_i[7:0]);
+ 16'b1001????????????:
+ $display ("\tdec\t$%0s,\t%d",
+ get_regname(ifid_insn_i[11:8]),
+ ifid_insn_i[7:0]);
+ 16'b1010????????????:
+ $display ("\tgsr");
+ 16'b1011????????????:
+ $display ("\tssr");
+ 16'b110000??????????:
+ $display ("\tbeq");
+ 16'b110001??????????:
+ $display ("\tbne");
+ 16'b110010??????????:
+ $display ("\tblt");
+ 16'b110011??????????:
+ $display ("\tbgt");
+ 16'b110100??????????:
+ $display ("\tbltu");
+ 16'b110101??????????:
+ $display ("\tbgtu");
+ 16'b110110??????????:
+ $display ("\tbge");
+ 16'b110111??????????:
+ $display ("\tble");
+ 16'b111000??????????:
+ $display ("\tbgeu");
+ 16'b111001??????????:
+ $display ("\tbleu");
+ 16'b111010??????????:
+ $display ("\tbad");
+ 16'b111011??????????:
+ $display ("\tbad");
+ 16'b111100??????????:
+ $display ("\tbad");
+ 16'b111101??????????:
+ $display ("\tbad");
+ 16'b111110??????????:
+ $display ("\tbad");
+ 16'b111111??????????:
+ $display ("\tbad");
+ endcase // casex (ifid_insn_i)
+
+ end
+ end
+
+endmodule // cpu_idecode
View
227 moxie/rtl/verilog/cpu_ifetch.v
@@ -0,0 +1,227 @@
+// cpu_ifetch.v - The instruction fetch unit.
+//
+// Copyright (c) 2009 Anthony Green. All Rights Reserved.
+// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
+//
+// The above named program is free software; you can redistribute it
+// and/or modify it under the terms of the GNU General Public License
+// version 2 as published by the Free Software Foundation.
+//
+// The above named program is distributed in the hope that it will be
+// useful, but WITHOUT ANY WARRANTY; without even the implied warranty
+// of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this work; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+// 02110-1301, USA.
+
+// Set the boot address upon system reset
+`define BOOT_ADDRESS 32'h00001000
+
+module cpu_ifetch (/*AUTOARG*/
+ // Outputs
+ ifid_insn_o, ifid_insn_data_o, ifid_insn_valid_o,
+ ifid_insn_data_valid_o,
+ // Inputs
+ rst_i, clk_i, idif_used_insn_i, idif_used_data_i
+ );
+
+ // --- Clock and Reset ------------------------------------------
+ input rst_i, clk_i;
+
+ // --- Instruction Buffer ---------------------------------------
+ reg[63:0] IB; // Instruction Buffer
+
+ // --- Inputs from Instruction Decoder --------------------------
+ input idif_used_insn_i, idif_used_data_i;
+
+ // --- Instruction Buffer ---------------------------------------
+ output [15:0] ifid_insn_o;
+ output [31:0] ifid_insn_data_o;
+ output ifid_insn_valid_o, ifid_insn_data_valid_o;
+ reg [15:0] ifid_insn_o;
+ reg [31:0] ifid_insn_data_o;
+ reg [0:0] ifid_insn_valid_o;
+ reg [0:0] ifid_insn_data_valid_o;
+
+ // --- Instruction Buffer ---------------------------------------
+ reg [63:0] ibuf_o;
+ wire [3:0] pc_index;
+ reg [3:0] pc_index_reg;
+
+ // --- Instruction Fetch state ----------------------------------
+ reg [1:0] if_state;
+ wire [1:0] if_next_state;
+ reg [2:0] if_IB_index;
+ reg [1:0] idif_read_word_0;
+ reg [1:0] idif_read_word_1;
+
+ // --- Test memory. Let's just read from an internal array. */
+ reg [7:0] MEM [0:128000];
+ reg [31:0] PC; /* For testing only. */
+
+ initial
+ begin
+ $readmemh("hello.vh", MEM);
+ end
+
+ // --- Combinational Logic --------------------------------------
+ assign pc_index = (rst_i == 0 ? (pc_index_reg
+ + (idif_used_insn_i ? 1 : 0)
+ + (idif_used_data_i ? 2 : 0)) % 4
+ : 0);
+
+ // --- Reset Logic ----------------------------------------------
+ always @ (posedge clk_i) begin
+ // Initialize all the registers
+ if (rst_i == 1) begin
+
+ // Initialize the Instruction Fetch state
+ if_state <= 0;
+ if_IB_index <= 0;
+ idif_read_word_0 <= 0;
+ idif_read_word_1 <= 0;
+
+ PC <= `BOOT_ADDRESS;
+ pc_index_reg <= 0;
+ end
+ end
+
+ /* Instructions may be as long as 48-bits, however we only
+ * have a 32-bit path to instruction memory. So, let's maintain a
+ * circular 64-bit instruction buffer (IB) and a state
+ * machine to control reads into that buffer.
+ *
+ * Our state machine has 16 states. The top row in the
+ * following table is a bitmap, where 0 represents an empty 32-bit
+ * word in the IB, and 1 is a valid 32-bit word. The column
+ * on the left hand side indicates our current index into the
+ * IB in bits. For each cell in this table, 0 means fetch
+ * the lower 32-bit word and 1 means fetch the upper 32-bit word.
+ * x is an impossible state.
+ *
+ * 00 01 10 11
+ * 00 0 0 1 x
+ * 16 0 0 1 x
+ * 32 1 0 1 x
+ * 48 1 0 1 x
+ *
+ * During the INSTRUCTION DECODE stage, we will insert
+ * bubbles into the pipeline if we don't have enough valid
+ * bits in the IB. */
+
+ assign if_next_state = if_get_next_state(if_state, if_IB_index);
+
+ function [1:0] if_get_next_state;
+ input [1:0] state;
+ input [1:0] index;
+ case (state)
+ 2'b00:
+ if (index < 2) begin
+ if_get_next_state = 2'b10;
+ end else begin
+ if_get_next_state = 2'b01;
+ end
+ 2'b01:
+ // Read 0.
+ if_get_next_state = 2'b11;
+ 2'b10:
+ // Read 1
+ if_get_next_state = 2'b11;
+ 2'b11:
+ if_get_next_state = 2'b11;
+ endcase // case (state)
+ endfunction
+
+ always @ (posedge clk_i) begin
+ $display("pc_index = 0x%x\t: 0x%x\t0x%x\t0x%x\t0x%x", pc_index,
+ IB[15:0], IB[31:16], IB[47:32], IB[63:48]);
+
+ case (pc_index)
+ 2'b00:
+ begin
+ $display("A");
+ ifid_insn_o = IB[63:48];
+ ifid_insn_data_o = IB[47:16];
+ ifid_insn_valid_o = if_state[1] == 1;
+ ifid_insn_data_valid_o = if_state[0] == 1;
+ end
+ 2'b01:
+ begin
+ $display("B");
+ ifid_insn_o = IB[47:32];
+ ifid_insn_data_o = IB[31:0];
+ ifid_insn_valid_o = if_state[1] == 1;
+ ifid_insn_data_valid_o = if_state[0] == 1;
+ end
+ 2'b10:
+ begin
+ $display("C");
+ ifid_insn_o = IB[31:16];
+ ifid_insn_data_o[15:0] = IB[15:0];
+ ifid_insn_data_o[31:16] = IB[63:48];
+ ifid_insn_valid_o = if_state[0] == 1;
+ ifid_insn_data_valid_o = if_state[1] == 1;
+ end
+ 2'b11:
+ begin
+ $display("D");
+ ifid_insn_o = IB[15:0];
+ ifid_insn_data_o = IB[63:32];
+ ifid_insn_valid_o = if_state[0] == 1;
+ ifid_insn_data_valid_o = if_state[1] == 1;
+ end
+ endcase // case (pc_index)
+ pc_index_reg = pc_index;
+ $display("insn = 0x%x", ifid_insn_o);
+ $display("data = 0x%x", ifid_insn_data_o);
+ end
+
+ always @ (posedge clk_i) begin
+ $display("MEM[PC] = 0x%x", MEM[PC]);
+ $display("if_state = 0x%x", if_state);
+ if (if_state == 2'b00 && if_next_state == 2'b10)
+ begin
+ IB[63:56] = MEM[PC];
+ IB[55:48] = MEM[PC+1];
+ IB[47:40] = MEM[PC+2];
+ IB[39:32] = MEM[PC+3];
+ PC = PC+4;
+ end
+ else if (if_state == 2'b00 && if_next_state == 2'b01)
+ begin
+ IB[31:24] = MEM[PC];
+ IB[23:16] = MEM[PC+1];
+ IB[15:8] = MEM[PC+2];
+ IB[7:0] = MEM[PC+3];
+ PC = PC+4;
+ end
+ else if (if_state == 2'b01)
+ begin
+ IB[63:56] = MEM[PC];
+ IB[55:48] = MEM[PC+1];
+ IB[47:40] = MEM[PC+2];
+ IB[39:32] = MEM[PC+3];
+ PC = PC+4;
+ end
+ else if (if_state == 2'b10)
+ begin
+ IB[31:24] = MEM[PC];
+ IB[23:16] = MEM[PC+1];
+ IB[15:8] = MEM[PC+2];
+ IB[7:0] = MEM[PC+3];
+ PC = PC+4;
+ end
+ $display("IB = 0x%x", IB);
+
+ if (idif_read_word_0 == 1 && if_next_state == 2'b11)
+ if_state = 2'b01;
+ else if (idif_read_word_1 == 1 && if_next_state == 2'b11)
+ if_state = 2'b10;
+ else
+ if_state = if_next_state;
+ end
+
+endmodule // cpu_ifetch
View
6 moxie/rtl/verilog/hello.c
@@ -0,0 +1,6 @@
+#include <stdio.h>
+int main()
+{
+ puts("Hello World!");
+ return 0;
+}
View
1,075 moxie/rtl/verilog/hello.vh
@@ -0,0 +1,1075 @@
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