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RISC-V: KVM: Implement firmware events
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SBI PMU extension defines a set of firmware events which can provide
useful information to guests about number of SBI calls. As hypervisor
implements the SBI PMU extension, these firmware events corresponds
to ecall invocations between VS->HS mode. All other firmware events
will always report zero if monitored as KVM doesn't implement them.

Signed-off-by: Atish Patra <atishp@rivosinc.com>
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@atishp04
atishp04 committed Jul 16, 2022
1 parent 1613054 commit 84a3fd7
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Showing 5 changed files with 94 additions and 14 deletions.
12 changes: 12 additions & 0 deletions arch/riscv/include/asm/kvm_vcpu_pmu.h
View file
Expand Up @@ -14,18 +14,29 @@

#define RISCV_KVM_MAX_FW_CTRS 32

struct kvm_fw_event {
/* Current value of the event */
unsigned long value;

/* Event monitoring status */
bool started;
};

/* Per virtual pmu counter data */
struct kvm_pmc {
u8 idx;
struct kvm_vcpu *vcpu;
struct perf_event *perf_event;
uint64_t counter_val;
union sbi_pmu_ctr_info cinfo;
/* Monitoring event ID */
unsigned long event_idx;
};

/* PMU data structure per vcpu */
struct kvm_pmu {
struct kvm_pmc pmc[RISCV_MAX_COUNTERS];
struct kvm_fw_event fw_event[RISCV_KVM_MAX_FW_CTRS];
/* Number of the virtual firmware counters available */
int num_fw_ctrs;
/* Number of the virtual hardware counters available */
Expand All @@ -48,6 +59,7 @@ struct kvm_pmu {

#endif

int kvm_riscv_vcpu_pmu_incr_fw(struct kvm_vcpu *vcpu, enum sbi_pmu_fw_generic_events_t fid);
int kvm_riscv_vcpu_pmu_read_hpm(struct kvm_vcpu *vcpu, unsigned int csr_num,
unsigned long *val, unsigned long new_val,
unsigned long wr_mask);
Expand Down
2 changes: 1 addition & 1 deletion arch/riscv/include/asm/sbi.h
View file
Expand Up @@ -171,7 +171,7 @@ enum sbi_pmu_fw_generic_events_t {
SBI_PMU_FW_IPI_SENT = 6,
SBI_PMU_FW_IPI_RECVD = 7,
SBI_PMU_FW_FENCE_I_SENT = 8,
SBI_PMU_FW_FENCE_I_RECVD = 9,
SBI_PMU_FW_FENCE_I_RCVD = 9,
SBI_PMU_FW_SFENCE_VMA_SENT = 10,
SBI_PMU_FW_SFENCE_VMA_RCVD = 11,
SBI_PMU_FW_SFENCE_VMA_ASID_SENT = 12,
Expand Down
6 changes: 5 additions & 1 deletion arch/riscv/kvm/tlb.c
View file
Expand Up @@ -240,6 +240,7 @@ void kvm_riscv_local_tlb_sanitize(struct kvm_vcpu *vcpu)

void kvm_riscv_fence_i_process(struct kvm_vcpu *vcpu)
{
kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_FENCE_I_RCVD);
local_flush_icache_all();
}

Expand Down Expand Up @@ -323,15 +324,18 @@ void kvm_riscv_hfence_process(struct kvm_vcpu *vcpu)
d.addr, d.size, d.order);
break;
case KVM_RISCV_HFENCE_VVMA_ASID_GVA:
kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_HFENCE_VVMA_ASID_RCVD);
kvm_riscv_local_hfence_vvma_asid_gva(
READ_ONCE(v->vmid), d.asid,
d.addr, d.size, d.order);
break;
case KVM_RISCV_HFENCE_VVMA_ASID_ALL:
kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_HFENCE_VVMA_ASID_RCVD);
kvm_riscv_local_hfence_vvma_asid_all(
READ_ONCE(v->vmid), d.asid);
break;
case KVM_RISCV_HFENCE_VVMA_GVA:
kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_HFENCE_VVMA_RCVD);
kvm_riscv_local_hfence_vvma_gva(
READ_ONCE(v->vmid),
d.addr, d.size, d.order);
Expand Down Expand Up @@ -382,7 +386,7 @@ void kvm_riscv_fence_i(struct kvm *kvm,
unsigned long hbase, unsigned long hmask)
{
make_xfence_request(kvm, hbase, hmask, KVM_REQ_FENCE_I,
KVM_REQ_FENCE_I, NULL);
KVM_REQ_FENCE_I, NULL);
}

void kvm_riscv_hfence_gvma_vmid_gpa(struct kvm *kvm,
Expand Down
81 changes: 69 additions & 12 deletions arch/riscv/kvm/vcpu_pmu.c
View file
Expand Up @@ -168,21 +168,40 @@ static int pmu_get_pmc_index(struct kvm_pmu *pmu, unsigned long eidx,
return pmu_get_programmable_pmc_index(pmu, eidx, cbase, cmask);
}

int kvm_riscv_vcpu_pmu_incr_fw(struct kvm_vcpu *vcpu, enum sbi_pmu_fw_generic_events_t fid)
{
struct kvm_pmu *kvpmu = vcpu_to_pmu(vcpu);
struct kvm_fw_event *fevent;

if (!kvpmu || fid >= SBI_PMU_FW_MAX)
return -EINVAL;

fevent = &kvpmu->fw_event[fid];
if (fevent->started) {
fevent->value++;
}

return 0;
}

int kvm_riscv_vcpu_pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx,
unsigned long *out_val)
{
struct kvm_pmu *kvpmu = vcpu_to_pmu(vcpu);
struct kvm_pmc *pmc;
u64 enabled, running;
int fevent_code;

if (!kvpmu)
return -EINVAL;

pmc = &kvpmu->pmc[cidx];
if (!pmc->perf_event)
return -EINVAL;

pmc->counter_val += perf_event_read_value(pmc->perf_event, &enabled, &running);
if (pmc->cinfo.type == SBI_PMU_CTR_TYPE_FW) {
fevent_code = get_event_code(pmc->event_idx);
pmc->counter_val = kvpmu->fw_event[fevent_code].value;
} else if (pmc->perf_event)
pmc->counter_val += perf_event_read_value(pmc->perf_event, &enabled, &running);
*out_val = pmc->counter_val;

return 0;
Expand Down Expand Up @@ -237,6 +256,7 @@ int kvm_riscv_vcpu_pmu_ctr_start(struct kvm_vcpu *vcpu, unsigned long ctr_base,
struct kvm_pmu *kvpmu = vcpu_to_pmu(vcpu);
int i, num_ctrs, pmc_index;
struct kvm_pmc *pmc;
int fevent_code;

num_ctrs = kvpmu->num_fw_ctrs + kvpmu->num_hw_ctrs;
if (ctr_base + __fls(ctr_mask) >= num_ctrs)
Expand All @@ -250,7 +270,15 @@ int kvm_riscv_vcpu_pmu_ctr_start(struct kvm_vcpu *vcpu, unsigned long ctr_base,
pmc = &kvpmu->pmc[pmc_index];
if (flag & SBI_PMU_START_FLAG_SET_INIT_VALUE)
pmc->counter_val = ival;
if (pmc->perf_event) {
if (pmc->cinfo.type == SBI_PMU_CTR_TYPE_FW) {
fevent_code = get_event_code(pmc->event_idx);
if (fevent_code >= SBI_PMU_FW_MAX)
return -EINVAL;

kvpmu->fw_event[fevent_code].started = true;
kvpmu->fw_event[fevent_code].value = pmc->counter_val;
}
else if (pmc->perf_event) {
perf_event_period(pmc->perf_event, pmu_get_sample_period(pmc));
perf_event_enable(pmc->perf_event);
}
Expand All @@ -266,6 +294,7 @@ int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu, unsigned long ctr_base,
int i, num_ctrs, pmc_index;
u64 enabled, running;
struct kvm_pmc *pmc;
int fevent_code;

num_ctrs = kvpmu->num_fw_ctrs + kvpmu->num_hw_ctrs;
if ((ctr_base + __fls(ctr_mask)) >= num_ctrs)
Expand All @@ -277,16 +306,24 @@ int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu, unsigned long ctr_base,
if (!test_bit(pmc_index, kvpmu->used_pmc))
continue;
pmc = &kvpmu->pmc[pmc_index];
if (pmc->perf_event) {
if (pmc->cinfo.type == SBI_PMU_CTR_TYPE_FW) {
fevent_code = get_event_code(pmc->event_idx);
if (fevent_code >= SBI_PMU_FW_MAX)
return -EINVAL;
kvpmu->fw_event[fevent_code].started = false;
} else if (pmc->perf_event) {
/* Stop counting the counter */
perf_event_disable(pmc->perf_event);
if (flag & SBI_PMU_STOP_FLAG_RESET) {
/* Relase the counter if this is a reset request */
pmc->counter_val += perf_event_read_value(pmc->perf_event, &enabled, &running);
pmu_release_perf_event(pmc);
clear_bit(pmc_index, kvpmu->used_pmc);
}
}
if (flag & SBI_PMU_STOP_FLAG_RESET) {
pmc->event_idx = SBI_PMU_EVENT_IDX_INVALID;
clear_bit(pmc_index, kvpmu->used_pmc);
}
}

return 0;
Expand All @@ -302,14 +339,14 @@ int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu *vcpu, unsigned long ctr_ba
int num_ctrs, ctr_idx;
u32 etype = pmu_get_perf_event_type(eidx);
u64 config;
struct kvm_pmc *pmc;
struct kvm_pmc *pmc = NULL;
bool is_fevent;

num_ctrs = kvpmu->num_fw_ctrs + kvpmu->num_hw_ctrs;
if ((etype == PERF_TYPE_MAX) || ((ctr_base + __fls(ctr_mask)) >= num_ctrs))
return -EINVAL;
is_fevent = pmu_is_fw_event(eidx);

if (pmu_is_fw_event(eidx))
return -EOPNOTSUPP;
/*
* SKIP_MATCH flag indicates the caller is aware of the assigned counter for
* for this event. Just do a sanity check if it already marked used.
Expand All @@ -318,13 +355,23 @@ int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu *vcpu, unsigned long ctr_ba
if (!test_bit(ctr_base, kvpmu->used_pmc))
return -EINVAL;
ctr_idx = ctr_base;
goto match_done;
if (is_fevent)
goto perf_event_done;
else
goto match_done;
}

ctr_idx = pmu_get_pmc_index(kvpmu, eidx, ctr_base, ctr_mask);
if (ctr_idx < 0)
return -ENOTSUPP;

/*
* No need to create perf events for firmware events as the firmware counter
* is supposed to return the measurement of VS->HS mode invocations.
*/
if (is_fevent)
goto perf_event_done;

match_done:
pmc = &kvpmu->pmc[ctr_idx];
pmu_release_perf_event(pmc);
Expand Down Expand Up @@ -362,18 +409,24 @@ int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu *vcpu, unsigned long ctr_ba
return -ENOTSUPP;
}

set_bit(ctr_idx, kvpmu->used_pmc);
pmc->perf_event = event;
if (flag & SBI_PMU_CFG_FLAG_AUTO_START) {
perf_event_enable(pmc->perf_event);
}

perf_event_done:
if (!pmc)
pmc = &kvpmu->pmc[ctr_idx];
pmc->event_idx = eidx;
set_bit(ctr_idx, kvpmu->used_pmc);
return ctr_idx;
}

int kvm_riscv_vcpu_pmu_init(struct kvm_vcpu *vcpu)
{
int i = 0, num_hw_ctrs, num_fw_ctrs, hpm_width;
int i, num_hw_ctrs, num_fw_ctrs, hpm_width;
struct kvm_pmu *kvpmu = vcpu_to_pmu(vcpu);
struct kvm_pmc *pmc;

if (!kvpmu)
return -EINVAL;
Expand All @@ -393,6 +446,7 @@ int kvm_riscv_vcpu_pmu_init(struct kvm_vcpu *vcpu)
bitmap_zero(kvpmu->used_pmc, RISCV_MAX_COUNTERS);
kvpmu->num_hw_ctrs = num_hw_ctrs;
kvpmu->num_fw_ctrs = num_fw_ctrs;
memset(&kvpmu->fw_event, 0, SBI_PMU_FW_MAX * sizeof(struct kvm_fw_event));
/*
* There is no corelation betwen the logical hardware counter and virtual counters.
* However, we need to encode a hpmcounter CSR in the counter info field so that
Expand Down Expand Up @@ -443,7 +497,10 @@ void kvm_riscv_vcpu_pmu_deinit(struct kvm_vcpu *vcpu)
for_each_set_bit(i, kvpmu->used_pmc, RISCV_MAX_COUNTERS) {
pmc = &kvpmu->pmc[i];
pmu_release_perf_event(pmc);
pmc->counter_val = 0;
pmc->event_idx = SBI_PMU_EVENT_IDX_INVALID;
}
memset(&kvpmu->fw_event, 0, SBI_PMU_FW_MAX * sizeof(struct kvm_fw_event));
}

void kvm_riscv_vcpu_pmu_reset(struct kvm_vcpu *vcpu)
Expand Down
7 changes: 7 additions & 0 deletions arch/riscv/kvm/vcpu_sbi_replace.c
View file
Expand Up @@ -12,6 +12,7 @@
#include <asm/csr.h>
#include <asm/sbi.h>
#include <asm/kvm_vcpu_timer.h>
#include <asm/kvm_vcpu_pmu.h>
#include <asm/kvm_vcpu_sbi.h>

static int kvm_sbi_ext_time_handler(struct kvm_vcpu *vcpu, struct kvm_run *run,
Expand All @@ -25,6 +26,7 @@ static int kvm_sbi_ext_time_handler(struct kvm_vcpu *vcpu, struct kvm_run *run,
if (cp->a6 != SBI_EXT_TIME_SET_TIMER)
return -EINVAL;

kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_SET_TIMER);
#if __riscv_xlen == 32
next_cycle = ((u64)cp->a1 << 32) | (u64)cp->a0;
#else
Expand Down Expand Up @@ -55,6 +57,7 @@ static int kvm_sbi_ext_ipi_handler(struct kvm_vcpu *vcpu, struct kvm_run *run,
if (cp->a6 != SBI_EXT_IPI_SEND_IPI)
return -EINVAL;

kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_IPI_SENT);
kvm_for_each_vcpu(i, tmp, vcpu->kvm) {
if (hbase != -1UL) {
if (tmp->vcpu_id < hbase)
Expand All @@ -65,6 +68,7 @@ static int kvm_sbi_ext_ipi_handler(struct kvm_vcpu *vcpu, struct kvm_run *run,
ret = kvm_riscv_vcpu_set_interrupt(tmp, IRQ_VS_SOFT);
if (ret < 0)
break;
kvm_riscv_vcpu_pmu_incr_fw(tmp, SBI_PMU_FW_IPI_RECVD);
}

return ret;
Expand All @@ -89,13 +93,15 @@ static int kvm_sbi_ext_rfence_handler(struct kvm_vcpu *vcpu, struct kvm_run *run
switch (funcid) {
case SBI_EXT_RFENCE_REMOTE_FENCE_I:
kvm_riscv_fence_i(vcpu->kvm, hbase, hmask);
kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_FENCE_I_SENT);
break;
case SBI_EXT_RFENCE_REMOTE_SFENCE_VMA:
if (cp->a2 == 0 && cp->a3 == 0)
kvm_riscv_hfence_vvma_all(vcpu->kvm, hbase, hmask);
else
kvm_riscv_hfence_vvma_gva(vcpu->kvm, hbase, hmask,
cp->a2, cp->a3, PAGE_SHIFT);
kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_HFENCE_VVMA_SENT);
break;
case SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID:
if (cp->a2 == 0 && cp->a3 == 0)
Expand All @@ -106,6 +112,7 @@ static int kvm_sbi_ext_rfence_handler(struct kvm_vcpu *vcpu, struct kvm_run *run
hbase, hmask,
cp->a2, cp->a3,
PAGE_SHIFT, cp->a4);
kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_HFENCE_VVMA_ASID_SENT);
break;
case SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA:
case SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID:
Expand Down

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