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It's more of a question rather than an issue. I'm posting it here because it's specifically related to this repository rather than F1/HDK in general.
Are the maintainers okay with accepting a pull request for CL scripts that enable workflow through an alternative FPGA development tool (which has support for AWS F1 platform).
Disclaimer: I'm one of the key contributor of the tool and the tool is based off Xilinx Vivado (authorized by Xilinx, of course.)
The pull request is specific to Visual System Integrator support for AWS F1 platform and contains CL Scripts that automate the workflow for bitstream generation. Thus this repo seems like the natural place to put those scripts.
The text was updated successfully, but these errors were encountered:
Hello,
It's more of a question rather than an issue. I'm posting it here because it's specifically related to this repository rather than F1/HDK in general.
Are the maintainers okay with accepting a pull request for CL scripts that enable workflow through an alternative FPGA development tool (which has support for AWS F1 platform).
The development tool is Visual System Integrator (http://docs.systemviewinc.com) (AWS marketplace link: https://aws.amazon.com/marketplace/pp/B071Z6QDFP?qid=1496280052532).
Disclaimer: I'm one of the key contributor of the tool and the tool is based off Xilinx Vivado (authorized by Xilinx, of course.)
The pull request is specific to Visual System Integrator support for AWS F1 platform and contains CL Scripts that automate the workflow for bitstream generation. Thus this repo seems like the natural place to put those scripts.
The text was updated successfully, but these errors were encountered: