axelitama / Progetto-Reti-Logiche-2020-2021 Public

Notifications You must be signed in to change notification settings
Fork 0
Star 1

Final project of the course Reti Logiche (Digital Logic Design) at Politecnico di Milano

1 star 0 forks Branches Tags Activity

Notifications

Name		Name	Last commit message	Last commit date
Latest commit History 4 Commits
deliverables		deliverables
README.md		README.md
project_reti_logiche.vhd		project_reti_logiche.vhd
relazione.pdf		relazione.pdf

Repository files navigation

Progetto-Reti-Logiche-2020-2021

Final project of the course Reti Logiche (Digital Logic Design) at Politecnico di Milano

About

Final project of the course Reti Logiche (Digital Logic Design) at Politecnico di Milano

vhdl university-project digital-logic polimi equalizer politecnico-di-milano digital-logic-design equalization

Report repository

Languages

VHDL 100.0%