ghdl / ghdl

692

VHDL 2008/93/87 simulator

vhdl

Good first issues

Landing site for GHDL

Documentation Discussion

#506 opened over 1 year ago by 1138-4EB

15

VHDL Updated May 4, 2019

clash-lang / clash-compiler

659

CAES Language for Synchronous Hardware

haskell hardware-description-language fpga vhdl verilog systemverilog

Haskell Updated May 3, 2019

SpinalHDL / VexRiscv

499

A FPGA friendly 32 bit RISC-V CPU implementation

riscv soc cpu spinalhdl vhdl verilog fpga softcore

Assembly Updated May 1, 2019

SpinalHDL / SpinalHDL

324

SpinalHDL core

scala rtl vhdl verilog fpga

Scala Updated May 3, 2019

VUnit / vunit

289

VUnit is a unit testing framework for VHDL/SystemVerilog

vhdl verification systemverilog-hdl unit-testing fpga asic testbench

Good first issues

SystemVerilog: Get current test name

good first issue enhancement

#307 opened over 1 year ago by alinaivanovaoff

8

VHDL Updated Apr 30, 2019

nickg / nvc

281

VHDL compiler and simulator

vhdl

VHDL Updated May 1, 2019

VLSI-EDA / PoC

243

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Com…

VHDL Updated Apr 13, 2019

sergeykhbr / riscv_vhdl

212

VHDL implementation of the RISC-V System-on-Chip based on bare "Rocket Chip".

riscv soc vhdl fpga-soc simulator systemc qt5

Verilog Updated May 4, 2019

howerj / forth-cpu

149

A Forth CPU and System on a Chip, based on the J1, written in VHDL

vhdl forth simulator target-board board processor cpu c softcore

VHDL Updated Apr 17, 2019

fabioperez / space-invaders-vhdl

131

Space Invaders game implemented with VHDL

vhdl games hardware fpga

VHDL Updated Feb 10, 2016

skordal / potato

112

A simple RISC-V processor for use in FPGA designs.

processor risc-v vhdl

VHDL Updated Oct 20, 2018

nitram2342 / degate

102

Open source software for chip reverse engineering.

chip vlsi verilog vhdl visualization gui library image-processing image-recognition reverse-engineering

C++ Updated Sep 23, 2018

forflo / yodl

91

A VHDL frontend for Yosys

vhdl yosys

C++ Updated Feb 27, 2017

drom / awesome-hdl

82

Hardware Description Languages

awesome awesome-list hardware-description-language verilog vhdl hdl

Updated Apr 24, 2019

OSVVM / OSVVM

75

Open Source VHDL Verification Methodology (OSVVM) Repository

verification-methodologies testbench coverage vhdl constrained-random simulation verification alerts memory memory-model scoreboard osvvm transaction-interfaces

VHDL Updated Mar 18, 2019

inmcm / Simon_Speck_Ciphers

54

Implementations of the Simon and Speck Block Ciphers

cryptography vhdl python c security fpga nsa block-ciphers cipher-s encryption decryption

VHDL Updated Jul 21, 2018

wfjm / w11

49

PDP-11/70 CPU core and SoC

retrocomputing pdp-11 fpga vhdl

VHDL Updated Apr 28, 2019

DreamIP / haddoc2

43

Caffe to VHDL - by DREAM research group

cnn caffe vhdl fpga hardware

VHDL Updated Nov 20, 2018

suoto / vim-hdl

41

Vim plugin to aid VHDL development

vim-plugins vhdl syntastic altera modelsim xilinx verilog systemverilog productivity syntax-checker

Python Updated Apr 29, 2019

olofk / edalize

41

An abstraction library for interfacing EDA tools

Python Updated May 3, 2019

SteffenReith / J1Sc

39

A reimplementation of a tiny stack CPU

fpga spinalhdl forth cpu vhdl verilog hdl j1-cpu

Scala Updated Mar 20, 2019

pedrorivera / SiaFpgaMiner

39

VHDL FPGA design of an optimized Blake2b pipeline to mine Siacoin

siacoin mining cryptocurrency blake2b vhdl

VHDL Updated Feb 7, 2018

kraigher / rust_hdl

38

vhdl language-server vhdl-parser vhdl-language-server parser rust-programming-language

Good first issues

Create NeoVim integration

good first issue help wanted

#10 opened 5 months ago by kraigher

1

Rust Updated May 2, 2019

timvideos / getting-started

38

List of ideas for getting started with TimVideos projects

gsoc gsoc-2016 gsoc-2017 fpga electronics university verilog vhdl projects hdmi video mjpeg usb usb-devices webcam hdmi2usb risc-v or1k

Shell Updated May 4, 2019

stnolting / neo430

36

A very small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-indep…

vhdl fpga soft-core microcontroller msp430 gcc customizable processor

VHDL Updated Jan 19, 2019

Domipheus / RPU

34

Basic RISC-V CPU implementation in VHDL.

fpga cpu vhdl risc-v riscv apache2-license

VHDL Updated Dec 14, 2018

jofrfu / tinyTPU

33

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

VHDL Updated Jan 5, 2019

VHDL / awesome-vhdl

31

A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.

awesome vhdl collection vhdl-library vhdl-collection vhdl-ip-core

Updated Sep 2, 2018

Paebbels / JSON-for-VHDL

30

A JSON library implemented in VHDL.

vhdl json parser fileformat fpga xilinx lattice modelsim questasim ghdl simulation synthesis

VHDL Updated May 23, 2018

kevinpt / symbolator

29

HDL symbol generator

hdl vhdl verilog symbol

Python Updated Oct 19, 2017

vhdl

Repositories 747

ghdl / ghdl

Good first issues

Landing site for GHDL

clash-lang / clash-compiler

SpinalHDL / VexRiscv

SpinalHDL / SpinalHDL

VUnit / vunit

Good first issues

SystemVerilog: Get current test name

nickg / nvc

VLSI-EDA / PoC

sergeykhbr / riscv_vhdl

howerj / forth-cpu

fabioperez / space-invaders-vhdl

skordal / potato

nitram2342 / degate

forflo / yodl

drom / awesome-hdl

OSVVM / OSVVM

inmcm / Simon_Speck_Ciphers

wfjm / w11

DreamIP / haddoc2

suoto / vim-hdl

olofk / edalize

SteffenReith / J1Sc

pedrorivera / SiaFpgaMiner

kraigher / rust_hdl

Good first issues

Create NeoVim integration

timvideos / getting-started

stnolting / neo430

Domipheus / RPU

jofrfu / tinyTPU

VHDL / awesome-vhdl

Paebbels / JSON-for-VHDL

kevinpt / symbolator

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