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Add rk3328-gmac support
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@ayufan
ayufan committed Aug 17, 2017
1 parent aa6aaf9 commit 956d6fc
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Showing 11 changed files with 590 additions and 8 deletions.
87 changes: 87 additions & 0 deletions arch/arm/dts/rk3328-evb.dts
View file
Expand Up @@ -15,6 +15,20 @@
stdout-path = &uart2;
};

gmac_clkin: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "gmac_clkin";
#clock-cells = <0>;
};

vcc_phy: vcc-phy-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_phy";
regulator-always-on;
regulator-boot-on;
};

vcc3v3_sdmmc: sdmmc-pwren {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
Expand Down Expand Up @@ -87,3 +101,76 @@
vbus-supply = <&vcc5v0_host_xhci>;
status = "okay";
};

&gmac2io {
phy-supply = <&vcc_phy>;
phy-mode = "rgmii";
clock_in_out = "input";
snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
pinctrl-names = "default";
pinctrl-0 = <&rgmiim1_pins>;
tx_delay = <0x26>;
rx_delay = <0x11>;
status = "okay";
};

&spi0 {
status = "okay";

/* SPI DMA does not work currently */
/delete-property/ dmas;
/delete-property/ #dma-cells;
/delete-property/ dma-names;

spi-flash@0 {
#address-cells = <0x1>;
#size-cells = <1>;
compatible = "st,m25p128", "spi-flash";
reg = <0x0>;
spi-max-frequency = <25000000>;
status = "okay";
m25p,fast-read;

partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;

system@0 {
label = "system";
reg = <0x0 0x8000>;
read-only;
};

loader@8000 {
label = "loader";
reg = <0x8000 0x3F8000>;
};

reserved@400000 {
label = "reserved";
reg = <0x400000 0x3C0000>;
read-only;
};

vendor@7c0000 {
label = "vendor";
reg = <0x7C0000 0x40000>;
};

uboot@800000 {
label = "uboot";
reg = <0x800000 0x400000>;
};

atf@c00000 {
label = "atf";
reg = <0xC00000 0x400000>;
};
};
};
};
19 changes: 19 additions & 0 deletions arch/arm/dts/rk3328.dtsi
View file
Expand Up @@ -456,6 +456,25 @@
status = "disabled";
};

gmac2io: ethernet@ff540000 {
compatible = "rockchip,rk3328-gmac";
reg = <0x0 0xff540000 0x0 0x10000>;
rockchip,grf = <&grf>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
<&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
<&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
<&cru PCLK_MAC2IO>;
clock-names = "stmmaceth", "mac_clk_rx",
"mac_clk_tx", "clk_mac_ref",
"clk_mac_refout", "aclk_mac",
"pclk_mac";
resets = <&cru SRST_GMAC2IO_A>;
reset-names = "stmmaceth";
status = "disabled";
};

usb_host0_ehci: usb@ff5c0000 {
compatible = "generic-ehci";
reg = <0x0 0xff5c0000 0x0 0x10000>;
Expand Down
164 changes: 164 additions & 0 deletions arch/arm/include/asm/arch-rockchip/grf_rk3328.h
View file
Expand Up @@ -145,6 +145,74 @@ enum {
GPIO0A7_SEL_MASK = 3 << GPIO0A7_SEL_SHIFT,
GPIO0A7_EMMC_DATA0 = 2,

GPIO0B0_SEL_SHIFT = 0,
GPIO0B0_SEL_MASK = 3 << GPIO0B0_SEL_SHIFT,
GPIO0B0_MAC_TXCLK = 1,

GPIO0B1_SEL_SHIFT = 2,
GPIO0B1_SEL_MASK = 3 << GPIO0B1_SEL_SHIFT,
GPIO0B1_MAC_CRS = 1,

GPIO0B2_SEL_SHIFT = 4,
GPIO0B2_SEL_MASK = 3 << GPIO0B2_SEL_SHIFT,
GPIO0B2_MAC_RXCLK = 1,

GPIO0B3_SEL_SHIFT = 6,
GPIO0B3_SEL_MASK = 3 << GPIO0B3_SEL_SHIFT,
GPIO0B3_MAC_MDIO = 1,

GPIO0B4_SEL_SHIFT = 8,
GPIO0B4_SEL_MASK = 3 << GPIO0B4_SEL_SHIFT,
GPIO0B4_MAC_TXEN = 1,

GPIO0B6_SEL_SHIFT = 12,
GPIO0B6_SEL_MASK = 3 << GPIO0B6_SEL_SHIFT,
GPIO0B6_MAC_RXD1 = 1,

GPIO0B7_SEL_SHIFT = 14,
GPIO0B7_SEL_MASK = 3 << GPIO0B7_SEL_SHIFT,
GPIO0B7_MAC_RXD0 = 1,

GPIO0C0_SEL_SHIFT = 0,
GPIO0C0_SEL_MASK = 3 << GPIO0C0_SEL_SHIFT,
GPIO0C0_MAC_TXD1 = 1,

GPIO0C1_SEL_SHIFT = 2,
GPIO0C1_SEL_MASK = 3 << GPIO0C1_SEL_SHIFT,
GPIO0C1_MAC_TXD0 = 1,

GPIO0C2_SEL_SHIFT = 4,
GPIO0C2_SEL_MASK = 3 << GPIO0C2_SEL_SHIFT,
GPIO0C2_MAC_COL = 1,

GPIO0C3_SEL_SHIFT = 6,
GPIO0C3_SEL_MASK = 3 << GPIO0C3_SEL_SHIFT,
GPIO0C3_MAC_MDC = 1,

GPIO0C4_SEL_SHIFT = 8,
GPIO0C4_SEL_MASK = 3 << GPIO0C4_SEL_SHIFT,
GPIO0C4_MAC_RXD3 = 1,

GPIO0C5_SEL_SHIFT = 10,
GPIO0C5_SEL_MASK = 3 << GPIO0C5_SEL_SHIFT,
GPIO0C5_MAC_RXD2 = 1,

GPIO0C6_SEL_SHIFT = 12,
GPIO0C6_SEL_MASK = 3 << GPIO0C6_SEL_SHIFT,
GPIO0C6_MAC_TXD2 = 1,

GPIO0C7_SEL_SHIFT = 14,
GPIO0C7_SEL_MASK = 3 << GPIO0C7_SEL_SHIFT,
GPIO0C7_MAC_TXD3 = 1,

GPIO0D0_SEL_SHIFT = 0,
GPIO0D0_SEL_MASK = 3 << GPIO0D0_SEL_SHIFT,
GPIO0D0_MAC_CLK = 1,

GPIO0D1_SEL_SHIFT = 2,
GPIO0D1_SEL_MASK = 3 << GPIO0D1_SEL_SHIFT,
GPIO0D1_MAC_RXDV = 1,

/* GPIO0D_IOMUX*/
GPIO0D6_SEL_SHIFT = 12,
GPIO0D6_SEL_MASK = 3 << GPIO0D6_SEL_SHIFT,
Expand All @@ -156,6 +224,77 @@ enum {
GPIO1A0_SEL_MASK = 0x3fff << GPIO1A0_SEL_SHIFT,
GPIO1A0_CARD_DATA_CLK_CMD_DETN = 0x1555,

/* GPIO1B_IOMUX */
GPIO1B0_SEL_SHIFT = 0,
GPIO1B0_SEL_MASK = 3 << GPIO1B0_SEL_SHIFT,
GPIO1B0_MAC_TXD1 = 2,

GPIO1B1_SEL_SHIFT = 2,
GPIO1B1_SEL_MASK = 3 << GPIO1B1_SEL_SHIFT,
GPIO1B1_MAC_TXD0 = 2,

GPIO1B2_SEL_SHIFT = 4,
GPIO1B2_SEL_MASK = 3 << GPIO1B2_SEL_SHIFT,
GPIO1B2_MAC_RXD1 = 2,

GPIO1B3_SEL_SHIFT = 6,
GPIO1B3_SEL_MASK = 3 << GPIO1B3_SEL_SHIFT,
GPIO1B3_MAC_RXD0 = 2,

GPIO1B4_SEL_SHIFT = 8,
GPIO1B4_SEL_MASK = 3 << GPIO1B4_SEL_SHIFT,
GPIO1B4_MAC_TXCLK = 2,

GPIO1B5_SEL_SHIFT = 10,
GPIO1B5_SEL_MASK = 3 << GPIO1B5_SEL_SHIFT,
GPIO1B5_MAC_RXCLK = 2,

GPIO1B6_SEL_SHIFT = 12,
GPIO1B6_SEL_MASK = 3 << GPIO1B6_SEL_SHIFT,
GPIO1B6_MAC_RXD3 = 2,

GPIO1B7_SEL_SHIFT = 14,
GPIO1B7_SEL_MASK = 3 << GPIO1B7_SEL_SHIFT,
GPIO1B7_MAC_RXD2 = 2,

/* GPIO1C_IOMUX */
GPIO1C0_SEL_SHIFT = 0,
GPIO1C0_SEL_MASK = 3 << GPIO1C0_SEL_SHIFT,
GPIO1C0_MAC_TXD3 = 2,

GPIO1C1_SEL_SHIFT = 2,
GPIO1C1_SEL_MASK = 3 << GPIO1C1_SEL_SHIFT,
GPIO1C1_MAC_TXD2 = 2,

GPIO1C2_SEL_SHIFT = 4,
GPIO1C2_SEL_MASK = 3 << GPIO1C2_SEL_SHIFT,
GPIO1C2_MAC_CRS = 2,

GPIO1C3_SEL_SHIFT = 6,
GPIO1C3_SEL_MASK = 3 << GPIO1C3_SEL_SHIFT,
GPIO1C3_MAC_MDIO = 2,

GPIO1C4_SEL_SHIFT = 8,
GPIO1C4_SEL_MASK = 3 << GPIO1C4_SEL_SHIFT,
GPIO1C4_MAC_COL = 2,

GPIO1C5_SEL_SHIFT = 10,
GPIO1C5_SEL_MASK = 3 << GPIO1C5_SEL_SHIFT,
GPIO1C5_MAC_CLK = 2,

GPIO1C6_SEL_SHIFT = 12,
GPIO1C6_SEL_MASK = 3 << GPIO1C6_SEL_SHIFT,
GPIO1C6_MAC_RXDV = 2,

GPIO1C7_SEL_SHIFT = 14,
GPIO1C7_SEL_MASK = 3 << GPIO1C7_SEL_SHIFT,
GPIO1C7_MAC_MDC = 2,

/* GPIO1D_IOMUX */
GPIO1D1_SEL_SHIFT = 2,
GPIO1D1_SEL_MASK = 3 << GPIO1D1_SEL_SHIFT,
GPIO1D1_MAC_TXEN = 2,

/* GPIO2A_IOMUX */
GPIO2A0_SEL_SHIFT = 0,
GPIO2A0_SEL_MASK = 3 << GPIO2A0_SEL_SHIFT,
Expand Down Expand Up @@ -245,4 +384,29 @@ enum {
IOMUX_SEL_SDMMC_M1,
};

#ifndef GPIO_BIAS_MASK
/* GPIO Bias settings */
enum GPIO_BIAS {
GPIO_BIAS_2MA = 0,
GPIO_BIAS_4MA,
GPIO_BIAS_8MA,
GPIO_BIAS_12MA,
};

#define GPIO_BIAS_MASK 0x3
#define GPIO_BIAS_SHIFT(x) ((x) * 2)
#endif

#ifndef GPIO_PULL_MASK
enum GPIO_PU_PD {
GPIO_PULL_NORMAL = 0,
GPIO_PULL_UP,
GPIO_PULL_DOWN,
GPIO_PULL_REPEAT,
};

#define GPIO_PULL_MASK 0x3
#define GPIO_PULL_SHIFT(x) ((x) * 2)
#endif

#endif /* __SOC_ROCKCHIP_RK3328_GRF_H__ */
11 changes: 11 additions & 0 deletions configs/evb-rk3328_defconfig
View file
Expand Up @@ -19,14 +19,23 @@ CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MTD=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_ROCKCHIP_RK3328=y
CONFIG_REGULATOR_PWM=y
Expand All @@ -37,6 +46,7 @@ CONFIG_DEBUG_UART_BASE=0xFF130000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
Expand All @@ -55,3 +65,4 @@ CONFIG_G_DNL_VENDOR_NUM=0x2207
CONFIG_G_DNL_PRODUCT_NUM=0x330a
CONFIG_USE_TINY_PRINTF=y
CONFIG_ERRNO_STR=y
CONFIG_CMD_ETHSW=y
4 changes: 4 additions & 0 deletions configs/evb-rk3399_defconfig
View file
Expand Up @@ -70,3 +70,7 @@ CONFIG_VIDEO_ROCKCHIP_MAX_YRES=1200
CONFIG_DISPLAY_ROCKCHIP_MIPI=y
CONFIG_USE_TINY_PRINTF=y
CONFIG_ERRNO_STR=y
CONFIG_MTD=y
CONFIG_ST_SMI=y
CONFIG_MTD_PARTITIONS=y
CONFIG_FLASH_CFI_LEGACY=y

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