Configurable Logic Block (CLB) design using Look Up Table (LUT) for utilization in Field Programmable Gate Array (FPGA) , made using System Verilog (SV)
Was curious about how a single FPGA board (Field Programmable Gate Array) can be programmed into behaving like any other digital circuit possible . Wanted to make one myself . So here am I .
FPGA are made up of smaller blocks called CONFIGURABLE LOGIC BLOCK (CLB) which can be interconnected to each other by giving signals to Transmission gates and completing the circuit .
The exact structure of CLB's are kept private by big companies like Xilinx , however it is established that CLB's are essentially built up of LOOK UP TABLE (LUT) . I decided to build a simple CLB , consisting of a LUT , a MUX , and a D Flip Flop .
Here is the design for CLB , rest of the code and design can be seen from the code section of the repository .
Here are the test results :
