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*.cache | ||
*.hw | ||
*.ip_user_files | ||
*.runs | ||
*.sim |
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# Active host test gateware | ||
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The plan is just a simple register interface to everything. | ||
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- A small state machine to control the USB-C side that can be | ||
controlled/queried via a few SPI registers. | ||
- The simplest possible register interface to the UART peripheral. | ||
- A register interface to control the io pins. | ||
Tests will be contained in... `tests/` and written in CocoTB. |
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rtl/active-host-test/active-host-test.srcs/constrs_1/new/test.xdc
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## Input clock (100MHz)... maybe it should be 25MHz or something? | ||
set_property IOSTANDARD LVCMOS33 [get_ports emcclk] | ||
set_property PACKAGE_PIN A10 [get_ports emcclk] | ||
create_clock -period 10.000 -name emcclk_100mhz -waveform {0.000 5.000} [get_ports emcclk] | ||
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#### All IO assignments below here are temporary and dependant on final schematic. | ||
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## UART Connections (to probe) | ||
# There's a way to do this, not sure if this is valid... | ||
set_property IOSTANDARD LVCMOS33 [get_ports sbu[*]] | ||
set_property PACKAGE_PIN K12 [get_ports sbu[1]] | ||
set_property PACKAGE_PIN L12 [get_ports sbu[0]] | ||
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## I2C Connections (to USB-C controller) | ||
set_property IOSTANDARD LVCMOS33 [get_ports i2c_sda] | ||
set_property IOSTANDARD LVCMOS33 [get_ports i2c_scl] | ||
set_property IOSTANDARD LVCMOS33 [get_ports i2c_int] | ||
set_property PACKAGE_PIN G14 [get_ports i2c_sda] | ||
set_property PACKAGE_PIN H14 [get_ports i2c_scl] | ||
set_property PACKAGE_PIN J14 [get_ports i2c_int] | ||
set_property PULLUP TRUE [get_ports i2c_sda] | ||
set_property PULLUP TRUE [get_ports i2c_scl] | ||
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## Power Gates | ||
set_property IOSTANDARD LVCMOS33 [get_ports probe_pwr_en] | ||
set_property IOSTANDARD LVCMOS33 [get_ports probe_vbus_en_b] | ||
set_property PACKAGE_PIN L14 [get_ports probe_pwr_en] | ||
set_property PACKAGE_PIN M14 [get_ports probe_vbus_en_b] | ||
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## SPI Device Interface | ||
set_property IOSTANDARD LVCMOS33 [get_ports spi_copi] | ||
set_property IOSTANDARD LVCMOS33 [get_ports spi_cipo] | ||
set_property IOSTANDARD LVCMOS33 [get_ports spi_cs] | ||
set_property IOSTANDARD LVCMOS33 [get_ports spi_clk] | ||
set_property PACKAGE_PIN N14 [get_ports spi_copi] | ||
set_property PACKAGE_PIN N13 [get_ports spi_cipo] | ||
set_property PACKAGE_PIN P13 [get_ports spi_cs] | ||
set_property PACKAGE_PIN P12 [get_ports spi_clk] | ||
set_property PULLUP TRUE [get_ports spi_cs] |
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rtl/active-host-test/active-host-test.srcs/sources_1/new/active_host.sv
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`timescale 1ns / 1ps | ||
`default_nettype none | ||
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`include "I2CTransceiver.svh" | ||
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module active_host#( | ||
parameter USB_CTRL_ADDR = 8'h44 | ||
) ( | ||
input wire emcclk, | ||
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// UART over SBU wires. | ||
// TX and RX depend on cable orientation thus these must be tri-stated. | ||
inout wire logic [1:0] sbu, | ||
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// USB-C Controller I2C Connection | ||
inout wire logic i2c_sda, | ||
output logic i2c_scl, | ||
input wire i2c_int, | ||
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// Power gating signals | ||
output logic probe_pwr_en, | ||
output logic probe_vbus_en_b, | ||
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// Control SPI interface | ||
input wire spi_copi, | ||
output logic spi_cipo, | ||
input wire spi_cs, | ||
input wire spi_clk | ||
); | ||
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// Reset control | ||
logic rst = 1; | ||
logic [3:0] rst_ctr = 0; | ||
always_ff @(posedge emcclk) begin : reset_p | ||
if (rst_ctr < 15) begin | ||
rst_ctr <= rst_ctr + 1; | ||
rst <= 1; | ||
end else begin | ||
rst <= 0; | ||
end | ||
end : reset_p | ||
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// --------- USB-C Control | ||
enum { | ||
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} usb_state; | ||
logic i2c_in_t i2c_cin; | ||
logic i2c_out_t i2c_cout; | ||
I2CTransceiver i2c_driver( | ||
.clk (emcclk ), | ||
.clkdiv (1000 ), // 100Mhz -> 100kHz | ||
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.i2c_scl (i2c_scl ), | ||
.i2c_sda (i2c_sda ), | ||
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.cin (i2c_cin ), | ||
.cout (i2c_cout ) | ||
); | ||
I2CRegisterHelper i2c_register( | ||
.clk (emcclk ), | ||
.slave_addr (USB_CTRL_ADDR ), | ||
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.request ( ), // NC - no arbiter | ||
.done ( ), // NC - no arbiter | ||
.ack (1'b1 ), // No arbiter - should always ACK | ||
.cin (i2c_cin ), | ||
.cout (i2c_cout ) | ||
); | ||
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always_ff @(posedge emcclk) begin : usb_c_p | ||
if (rst) begin | ||
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end else begin | ||
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end | ||
end : usb_c_p | ||
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endmodule | ||
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`default_nettype wire |
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