- Abstract
- Reference Circuit Diagram
- Reference Waveform
- Circuit Details
- Truth Table
- Software Used
- Circuit Diagram in eSim 2.3
- Verilog Code
- Makerchip
- Makerchip Plots
- Netlists
- NgSpice Plots
- Steps to run generate NgVeri Model
- Author
- Acknowlegdements
- References
A magnitude Comparator is a combinational circuit that compares two binary numbers in order to find out whether one binary number is equal, less than, or greater than the other binary number. The Circuit will have two inputs one for A and the other for B and have three output terminals, one for A > B condition, one for A = B condition, and one for A<B condition.
In the diagram, a 2-bit magnitude comparator is split into two blocks: digital and analog.
The digital portion of the circuit is implemented using Verilog.
For the analog portion, the two 3-input ”OR” gates and one 2-input ”AND” gate are replaced with NMOS and
PMOS transistors, making the circuit mixed-signal.
The output of the mixed signal 2-bit comparator
circuit may be less than, equal to (ET), or greater than.
| Input A1 | Input A0 | Input B1 | Input B0 | Output A<B | Output A=B | Output A>B |
|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 1 | 0 |
| 0 | 0 | 0 | 1 | 1 | 0 | 0 |
| 0 | 0 | 1 | 0 | 1 | 0 | 0 |
| 0 | 0 | 1 | 1 | 1 | 0 | 0 |
| 0 | 1 | 0 | 0 | 0 | 0 | 1 |
| 0 | 1 | 0 | 1 | 0 | 1 | 0 |
| 0 | 1 | 1 | 0 | 1 | 0 | 0 |
| 0 | 1 | 1 | 1 | 1 | 0 | 0 |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 |
| 1 | 0 | 0 | 1 | 0 | 0 | 1 |
| 1 | 0 | 1 | 0 | 0 | 1 | 0 |
| 1 | 0 | 1 | 1 | 1 | 0 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 1 |
| 1 | 1 | 0 | 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 0 | 0 | 0 | 1 |
| 1 | 1 | 1 | 0 | 0 | 0 | 1 |
| 1 | 1 | 1 | 1 | 0 | 1 | 0 |
It is an Open Source EDA developed by FOSSEE, IIT Bombay. It is used for electronic circuit simulation. It is made by the combination of two software namely NgSpice and KiCAD.
For more details refer:
https://esim.fossee.in/home
It is an Open Source Software for Spice Simulations. For more details refer:
http://ngspice.sourceforge.net/docs.html
It is an Online Web Browser IDE for Verilog/System-verilog/TL-Verilog Simulation. Refer
https://www.makerchip.com/
The following is the schematic in eSim:
\TLV_version 1d: tl-x.org
\SV
/* verilator lint_off UNUSED*/ /* verilator lint_off DECLFILENAME*/ /* verilator lint_off BLKSEQ*/ /* verilator lint_off WIDTH*/ /* verilator lint_off SELRANGE*/ /* verilator lint_off PINCONNECTEMPTY*/ /* verilator lint_off DEFPARAM*/ /* verilator lint_off IMPLICIT*/ /* verilator lint_off COMBDLY*/ /* verilator lint_off SYNCASYNCNET*/ /* verilator lint_off UNOPTFLAT */ /* verilator lint_off UNSIGNED*/ /* verilator lint_off CASEINCOMPLETE*/ /* verilator lint_off UNDRIVEN*/ /* verilator lint_off VARHIDDEN*/ /* verilator lint_off CASEX*/ /* verilator lint_off CASEOVERLAP*/ /* verilator lint_off PINMISSING*/ /* verilator lint_off BLKANDNBLK*/ /* verilator lint_off MULTIDRIVEN*/ /* verilator lint_off WIDTHCONCAT*/ /* verilator lint_off ASSIGNDLY*/ /* verilator lint_off MODDUP*/ /* verilator lint_off STMTDLY*/ /* verilator lint_off LITENDIAN*/ /* verilator lint_off INITIALDLY*/
//Your Verilog/System Verilog Code Starts Here:
module vishnu_2bitcomp(A1,A0,B1,B0,t0,t1,t2,t3,t4,t5,t6,t7);
input A1,A0,B1,B0;
output t0,t1,t2,t3,t4,t5,t6,t7;
and g1(t0,~A1,B1);
and g2(t1,~A0,B1,B0);
and g3(t2,~A1,~A0,B0);
xnor g4(t3,A1,B1);
xnor g5(t4,A0,B0);
and g6(t5,A1,~B1);
and g7(t6,A0,~B1,~B0);
and g8(t7,A1,A0,~B0);
endmodule
//Top Module Code Starts here:
module top(input logic clk, input logic reset, input logic [31:0] cyc_cnt, output logic passed, output logic failed);
logic A1;//input
logic A0;//input
logic B1;//input
logic B0;//input
logic t0;//output
logic t1;//output
logic t2;//output
logic t3;//output
logic t4;//output
logic t5;//output
logic t6;//output
logic t7;//output
//The $random() can be replaced if user wants to assign values
assign A1 = $random();
assign A0 = $random();
assign B1 = $random();
assign B0 = $random();
vishnu_2bitcomp vishnu_2bitcomp(.A1(A1), .A0(A0), .B1(B1), .B0(B0), .t0(t0), .t1(t1), .t2(t2), .t3(t3), .t4(t4), .t5(t5), .t6(t6), .t7(t7));
\TLV
//Add \TLV here if desired
\SV
endmodule
- Open eSim
- Run NgVeri-Makerchip
- Add top level verilog file in Makerchip Tab
- Click on NgVeri tab
- Add dependency files
- Click on Run Verilog to NgSpice Converter
- Debug if any errors
- Model created successfully
Vishnu Bajjuri, B.Tech (ECE), Jyothishmathi Institute of Technology and Science, Karimnagar.
- FOSSEE, IIT Bombay
- Steve Hoover, Founder, Redwood EDA
- Kunal Ghosh, Co-founder, VSD Corp. Pvt. Ltd. - kunalpghosh@gmail.com
- Sumanto Kar, eSim Team, FOSSEE
- https://www.c2s.gov.in/
- https://www.google.co.in/
- https://www.vlsisystemdesign.com/
- https://spoken-tutorial.org/
- Weste, Neil HE, and David Harris. CMOS VLSI design: a circuits and systems perspective. Pearson Education India, 2015.
- Mano, M. Morris. Digital logic and computer design. Pearson Education India, 2017
- https://www.geeksforgeeks.org/magnitude-comparator-in-digital-logic/