UCOMISS use wrong operand types

[Kashio]

Right now UCOMISS encoded with opcode F2 0F 2E use operand type ss for its operand of addressing W which is defined as:

Scalar element of a 128-bit packed single-precision floating data.

According to the intel docs:

Compares the single-precision floating-point values in the low doublewords of operand 1 (first operand) and operand 2 (second operand), and sets the ZF, PF, and CF flags in the EFLAGS register according to the result (unordered, greater than, less than, or equal). The OF, SF and AF flags in the EFLAGS register are set to 0. The unordered result is returned if either source operand is a NaN (QNaN or SNaN).
Operand 1 is an XMM register; operand 2 can be an XMM register or a 32 bit memory location.

Since it's only copying the lower 32 bits of the register and the memory variant is also referencing 32 bit memory the operand type should be of type d which is defined as:

Doubleword, regardless of operand-size attribute.

[BarebitOpenSource]

This one looks right. Refer to #23.

[BarebitOpenSource]

Feel free to reopen this issue if you still think the operand type is wrong.