msm8953 muxdiv fix

lk2nd/smp/clock-msm8953.c

@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/* Copyright (c) 2022, Stephan Gerhold <stephan@gerhold.net> */
+
+#include <board.h>
+#include <boot.h>
+#include <clock.h>
+#include <platform/iomap.h>
+#include <reg.h>
+
+#define MHZ				1000000
+
+static bool platform_has_second_cluster(void)
+{
+	switch (board_platform_id()) {
+		case MSM8953:
+		case SDM632:
+		case SDA632:
+			return true;
+		default:
+			/* MSM8916/MSM8936 have only one CPU cluster */
+			return false;
+	};
+}
+
+static int lk2nd_8953_clock_setup(void *dtb, const char *cmdline,
+				  enum boot_type boot_type)
+{
+
+	if (!platform_has_second_cluster())
+		return 0;
+
+	// select clock for secondary cluster
+	clk_get_set_enable("a53ssmux_c0", 800 * MHZ, 1);
+	return 0;
+}
+DEV_TREE_UPDATE(lk2nd_8953_clock_setup);

platform/msm8953/include/platform/iomap.h

@@ -52,6 +52,16 @@
 #define QTMR_BASE                          APPS_APCS_F0_QTMR_V1_BASE
 #define APCS_ALIAS0_IPC_INTERRUPT          (APPS_SS_BASE + 0x00111008)
 
+#define APCS_C0_GLB_BASE                   (APPS_SS_BASE + 0x111000)
+#define APCS_C0_CMD_RCGR                   (APCS_C1_GLB_BASE + 0x50)
+#define APCS_C0_CFG_RCGR                   (APCS_C1_GLB_BASE + 0x54)
+#define APCS_C0_PLL_BASE                   (APPS_SS_BASE + 0x116000)
+
+#define APCS_C1_GLB_BASE                   (APPS_SS_BASE + 0x011000)
+#define APCS_C1_CMD_RCGR                   (APCS_C0_GLB_BASE + 0x50)
+#define APCS_C1_CFG_RCGR                   (APCS_C0_GLB_BASE + 0x54)
+#define APCS_C1_PLL_BASE                   (APPS_SS_BASE + 0x016000)
+
 #define PERIPH_SS_BASE                     0x07800000
 
 #define MSM_SDC1_BASE                      (PERIPH_SS_BASE + 0x00024000)

platform/msm8953/msm8953-clock.c

@@ -364,6 +364,49 @@ static struct vote_clk gcc_blsp1_ahb_clk = {
 	},
 };
 
+/* Need different gpll0 source value for CPU clocks */
+#undef gpll0_source_val
+#define gpll0_source_val  4
+
+static struct clk_freq_tbl ftbl_a53ssmux[] =
+{
+	F( 19200000,    cxo,  1, 0, 0),
+	F(800000000,  gpll0,  1, 0, 0),
+	F_END
+};
+
+static struct rcg_clk a53ssmux_c0 =
+{
+	.cmd_reg      = (uint32_t *) APCS_C0_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) APCS_C0_CFG_RCGR,
+	.set_rate     = clock_lib2_rcg_set_rate_hid,
+	.freq_tbl     = ftbl_a53ssmux,
+	.current_freq = &rcg_dummy_freq,
+
+	.c = {
+		.dbg_name = "a53ssmux_c0",
+		.ops      = &clk_ops_rcg,
+	},
+};
+
+static struct rcg_clk a53ssmux_c1 =
+{
+	.cmd_reg      = (uint32_t *) APCS_C1_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) APCS_C1_CFG_RCGR,
+	.set_rate     = clock_lib2_rcg_set_rate_hid,
+	.freq_tbl     = ftbl_a53ssmux,
+	.current_freq = &rcg_dummy_freq,
+
+	.c = {
+		.dbg_name = "a53ssmux_c1",
+		.ops      = &clk_ops_rcg,
+	},
+};
+
+/* Restore original gpll0 source value */
+#undef gpll0_source_val
+#define gpll0_source_val  1
+
 /* USB Clocks */
 static struct branch_clk gcc_pc_noc_usb30_axi_clk =
 {
@@ -720,6 +763,9 @@ static struct clk_lookup msm_clocks_8953[] =
 	CLK_LOOKUP("ce1_axi_clk",  gcc_ce1_axi_clk.c),
 	CLK_LOOKUP("ce1_core_clk", gcc_ce1_clk.c),
 	CLK_LOOKUP("ce1_src_clk",  ce1_clk_src.c),
+
+	CLK_LOOKUP("a53ssmux_c0", a53ssmux_c0.c),
+	CLK_LOOKUP("a53ssmux_c1", a53ssmux_c1.c),
 };
 
 void platform_clock_init(void)