increased sine prescaler to 10bit (verilog)

src/bat52_pwm_ddpm_top.v

@@ -1,6 +1,6 @@
 // File: /media/marco/DATA/programming/rtl/ddpm/tt03-ddpm-pwm/src/myhdl/work_ddpm_top/bat52_pwm_ddpm_top.v
 // Generated by MyHDL 0.11.42
-// Date: Thu Mar 16 00:22:35 2023
+// Date: Sun Mar 26 16:27:09 2023
 
 
 `timescale 1ns/10ps
@@ -15,30 +15,31 @@ input [7:0] io_in;
 output [7:0] io_out;
 reg [7:0] io_out;
 
-wire [7:0] count_sine_out;
-wire [7:0] prescaler_out;
-reg [7:0] sine_out;
 reg clk;
 wire [5:0] count_out;
 reg ddpm;
 reg ddpm_sine;
 wire e;
 wire e_sine;
 reg [5:0] inval;
-reg prescaler_en;
 reg pwm;
 reg pwm_sine;
 reg resetn;
 wire sd;
 reg sd_sine;
+reg prescaler_en;
+wire [7:0] sine_in;
+wire [9:0] prescaler_out;
 wire [5:0] pwm_ddpm0_ddpm_int_all;
 reg [5:0] pwm_ddpm0_counter_down0_count;
-reg [7:0] counter_up0_count;
+reg [9:0] counter_up0_count;
 wire [1:0] sine_lut0_in_index_msb2;
 reg [6:0] sine_lut0_in_index_pi2;
 reg sine_lut0_sign;
+reg [7:0] sine_lut0_sine_out;
 wire [6:0] sine_lut0_sine_pi2;
 wire [447:0] sine_lut0_sine_lut_pi20_lut_module0_lut_c;
+wire [7:0] pwm_ddpm1_count_out;
 wire [7:0] pwm_ddpm1_ddpm_int_all;
 reg [7:0] pwm_ddpm1_counter_down1_count;
 reg [8:0] pwm_ddpm1_sd1_mod0_delta;
@@ -190,7 +191,7 @@ always @(negedge clk, negedge resetn) begin: BAT52_PWM_DDPM_TOP_COUNTER_UP0_COUN
     end
     else begin
         if (prescaler_en) begin
-            if (($signed({1'b0, counter_up0_count}) < (256 - 1))) begin
+            if (($signed({1'b0, counter_up0_count}) < (1024 - 1))) begin
                 counter_up0_count <= (counter_up0_count + 1);
             end
             else begin
@@ -209,18 +210,18 @@ end
 assign prescaler_out = counter_up0_count;
 
 
-always @(prescaler_out) begin: BAT52_PWM_DDPM_TOP_SINE_LUT0_GEN_INDEX_PI2_PROC
-    if ((prescaler_out[(8 - 2)] == 0)) begin
-        sine_lut0_in_index_pi2[(8 - 1)-1:0] = prescaler_out[(8 - 2)-1:0];
+always @(sine_in) begin: BAT52_PWM_DDPM_TOP_SINE_LUT0_GEN_INDEX_PI2_PROC
+    if ((sine_in[(8 - 2)] == 0)) begin
+        sine_lut0_in_index_pi2[(8 - 1)-1:0] = sine_in[(8 - 2)-1:0];
     end
     else begin
-        sine_lut0_in_index_pi2[(8 - 1)-1:0] = (63 - prescaler_out[(8 - 2)-1:0]);
+        sine_lut0_in_index_pi2[(8 - 1)-1:0] = (63 - sine_in[(8 - 2)-1:0]);
     end
 end
 
 
 
-assign sine_lut0_in_index_msb2 = prescaler_out[8-1:(8 - 2)];
+assign sine_lut0_in_index_msb2 = sine_in[8-1:(8 - 2)];
 
 
 always @(sine_lut0_in_index_msb2) begin: BAT52_PWM_DDPM_TOP_SINE_LUT0_GEN_INDEX_SIGN_PROC
@@ -239,10 +240,10 @@ assign sine_lut0_sine_pi2 = ((sine_lut0_sine_lut_pi20_lut_module0_lut_c >>> (sin
 
 always @(sine_lut0_sign, sine_lut0_sine_pi2) begin: BAT52_PWM_DDPM_TOP_SINE_LUT0_GEN_SINE_OUT_PROC
     if ((sine_lut0_sign == 0)) begin
-        sine_out = (127 + sine_lut0_sine_pi2);
+        sine_lut0_sine_out = (127 + sine_lut0_sine_pi2);
     end
     else begin
-        sine_out = (127 - sine_lut0_sine_pi2);
+        sine_lut0_sine_out = (127 - sine_lut0_sine_pi2);
     end
 end
 
@@ -264,11 +265,11 @@ end
 
 
 
-assign count_sine_out = pwm_ddpm1_counter_down1_count;
+assign pwm_ddpm1_count_out = pwm_ddpm1_counter_down1_count;
 
 
-always @(count_sine_out, sine_out) begin: BAT52_PWM_DDPM_TOP_PWM_DDPM1_PWM_PROC
-    if ((count_sine_out < sine_out)) begin
+always @(pwm_ddpm1_count_out, sine_lut0_sine_out) begin: BAT52_PWM_DDPM_TOP_PWM_DDPM1_PWM_PROC
+    if ((pwm_ddpm1_count_out < sine_lut0_sine_out)) begin
         pwm_sine = 1;
     end
     else begin
@@ -278,11 +279,11 @@ always @(count_sine_out, sine_out) begin: BAT52_PWM_DDPM_TOP_PWM_DDPM1_PWM_PROC
 end
 
 
-always @(count_sine_out, sine_out) begin: BAT52_PWM_DDPM_TOP_PWM_DDPM1_DDPM_INT_PROC
+always @(pwm_ddpm1_count_out, sine_lut0_sine_out) begin: BAT52_PWM_DDPM_TOP_PWM_DDPM1_DDPM_INT_PROC
     integer bidx;
     for (bidx=0; bidx<8; bidx=bidx+1) begin
-        if ((($signed({1'b0, count_sine_out}) & ((2 ** (8 - bidx)) - 1)) == (2 ** ((8 - 1) - bidx)))) begin
-            pwm_ddpm1_ddpm_int[bidx] = sine_out[bidx];
+        if ((($signed({1'b0, pwm_ddpm1_count_out}) & ((2 ** (8 - bidx)) - 1)) == (2 ** ((8 - 1) - bidx)))) begin
+            pwm_ddpm1_ddpm_int[bidx] = sine_lut0_sine_out[bidx];
         end
         else begin
             pwm_ddpm1_ddpm_int[bidx] = 0;
@@ -302,15 +303,15 @@ always @(pwm_ddpm1_ddpm_int_all) begin: BAT52_PWM_DDPM_TOP_PWM_DDPM1_DDPM_PROC
 end
 
 
-always @(sine_out, pwm_ddpm1_sd1_mod0_delta, pwm_ddpm1_sd1_mod0_qerr) begin: BAT52_PWM_DDPM_TOP_PWM_DDPM1_SD1_MOD0_SATURATED_ADDER0_DELTA_PROC
-    if (((sine_out + pwm_ddpm1_sd1_mod0_qerr) > (512 - 1))) begin
+always @(sine_lut0_sine_out, pwm_ddpm1_sd1_mod0_delta, pwm_ddpm1_sd1_mod0_qerr) begin: BAT52_PWM_DDPM_TOP_PWM_DDPM1_SD1_MOD0_SATURATED_ADDER0_DELTA_PROC
+    if (((sine_lut0_sine_out + pwm_ddpm1_sd1_mod0_qerr) > (512 - 1))) begin
         pwm_ddpm1_sd1_mod0_delta = (512 - 1);
     end
-    else if (((sine_out + pwm_ddpm1_sd1_mod0_qerr) < (0 + 1))) begin
+    else if (((sine_lut0_sine_out + pwm_ddpm1_sd1_mod0_qerr) < (0 + 1))) begin
         pwm_ddpm1_sd1_mod0_delta = (0 + 1);
     end
     else begin
-        pwm_ddpm1_sd1_mod0_delta = (sine_out + pwm_ddpm1_sd1_mod0_qerr);
+        pwm_ddpm1_sd1_mod0_delta = (sine_lut0_sine_out + pwm_ddpm1_sd1_mod0_qerr);
     end
 end
 
@@ -350,14 +351,18 @@ always @(count_out) begin: BAT52_PWM_DDPM_TOP_PRESCALER_EN_PROC
 end
 
 
+
+assign sine_in = prescaler_out[10-1:(10 - 8)];
+
+
 always @(io_in) begin: BAT52_PWM_DDPM_TOP_IN_PROC
     clk = io_in[0];
     resetn = io_in[1];
     inval[6-1:0] = io_in[8-1:2];
 end
 
 
-always @(sd, sd_sine, pwm, ddpm_sine, e_sine, e, ddpm, pwm_sine) begin: BAT52_PWM_DDPM_TOP_IO_OUT_PROC
+always @(ddpm_sine, ddpm, e_sine, sd_sine, pwm_sine, e, sd, pwm) begin: BAT52_PWM_DDPM_TOP_IO_OUT_PROC
     io_out[0] = pwm;
     io_out[1] = ddpm;
     io_out[2] = sd;

src/tb_bat52_pwm_ddpm_top.v

@@ -4,6 +4,8 @@ reg [7:0] io_in;
 wire [7:0] io_out;
 
 initial begin
+    $dumpfile("bat52_pwm_ddpm_top.vcd");
+    $dumpvars(0, dut);
     $from_myhdl(
         io_in
     );