Mipu

A Simple MISP CPU with cache written in Verilog.

This design is still in progress.

Introduction

It's my project of Computer Architecture in SMIE.

这是我的计算机组成原理这门课程的 Project，暂时是双路组相联的架构。

Declaration

If you want to use my code you should give clear reference in your lab report.

如果你在你的项目中有任何引用我的代码，请您在实验报告中说明，以免不必要的麻烦。

Detail

More information please visit My Blog.

更多细节请移步访问我的博客。