clk: bcm21664: add common bus clocks

Now that bus clock support has been implemented into the Broadcom Kona
clock driver, add bus clocks corresponding to SDIO, UART and BSC,
as well as the USB OTG bus clock.

Signed-off-by: Artur Weber <aweber.kernel@gmail.com>

drivers/clk/bcm/clk-bcm21664.c

@@ -54,6 +54,22 @@ static struct ccu_data aon_ccu_data = {
 
 /* Master CCU */
 
+static struct bus_clk_data sdio1_ahb_data = {
+	.gate		= HW_SW_GATE(0x0358, 16, 0, 1),
+};
+
+static struct bus_clk_data sdio2_ahb_data = {
+	.gate		= HW_SW_GATE(0x035c, 16, 0, 1),
+};
+
+static struct bus_clk_data sdio3_ahb_data = {
+	.gate		= HW_SW_GATE(0x0364, 16, 0, 1),
+};
+
+static struct bus_clk_data sdio4_ahb_data = {
+	.gate		= HW_SW_GATE(0x0360, 16, 0, 1),
+};
+
 static struct peri_clk_data sdio1_data = {
 	.gate		= HW_SW_GATE(0x0358, 18, 2, 3),
 	.clocks		= CLOCKS("ref_crystal",
@@ -122,13 +138,25 @@ static struct peri_clk_data sdio4_sleep_data = {
 	.gate		= HW_SW_GATE(0x0360, 18, 2, 3),
 };
 
+static struct bus_clk_data usb_otg_ahb_data = {
+	.gate		= HW_SW_GATE(0x0348, 16, 0, 1),
+};
+
 static struct ccu_data master_ccu_data = {
 	BCM21664_CCU_COMMON(master, MASTER),
 	.policy		= {
 		.enable		= CCU_LVM_EN(0x0034, 0),
 		.control	= CCU_POLICY_CTL(0x000c, 0, 1, 2),
 	},
 	.kona_clks	= {
+		[BCM21664_MASTER_CCU_SDIO1_AHB] =
+			KONA_CLK(master, sdio1_ahb, bus),
+		[BCM21664_MASTER_CCU_SDIO2_AHB] =
+			KONA_CLK(master, sdio2_ahb, bus),
+		[BCM21664_MASTER_CCU_SDIO3_AHB] =
+			KONA_CLK(master, sdio3_ahb, bus),
+		[BCM21664_MASTER_CCU_SDIO4_AHB] =
+			KONA_CLK(master, sdio4_ahb, bus),
 		[BCM21664_MASTER_CCU_SDIO1] =
 			KONA_CLK(master, sdio1, peri),
 		[BCM21664_MASTER_CCU_SDIO2] =
@@ -145,12 +173,26 @@ static struct ccu_data master_ccu_data = {
 			KONA_CLK(master, sdio3_sleep, peri),
 		[BCM21664_MASTER_CCU_SDIO4_SLEEP] =
 			KONA_CLK(master, sdio4_sleep, peri),
+		[BCM21664_MASTER_CCU_USB_OTG_AHB] =
+			KONA_CLK(master, usb_otg_ahb, bus),
 		[BCM21664_MASTER_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
 	},
 };
 
 /* Slave CCU */
 
+static struct bus_clk_data uartb_apb_data = {
+	.gate		= HW_SW_GATE_AUTO(0x0400, 16, 0, 1),
+};
+
+static struct bus_clk_data uartb2_apb_data = {
+	.gate		= HW_SW_GATE_AUTO(0x0404, 16, 0, 1),
+};
+
+static struct bus_clk_data uartb3_apb_data = {
+	.gate		= HW_SW_GATE_AUTO(0x0408, 16, 0, 1),
+};
+
 static struct peri_clk_data uartb_data = {
 	.gate		= HW_SW_GATE(0x0400, 18, 2, 3),
 	.clocks		= CLOCKS("ref_crystal",
@@ -181,6 +223,22 @@ static struct peri_clk_data uartb3_data = {
 	.trig		= TRIGGER(0x0afc, 4),
 };
 
+static struct bus_clk_data bsc1_apb_data = {
+	.gate = HW_SW_GATE_AUTO(0x0458, 16, 0, 1),
+};
+
+static struct bus_clk_data bsc2_apb_data = {
+	.gate = HW_SW_GATE_AUTO(0x045c, 16, 0, 1),
+};
+
+static struct bus_clk_data bsc3_apb_data = {
+	.gate = HW_SW_GATE_AUTO(0x0470, 16, 0, 1),
+};
+
+static struct bus_clk_data bsc4_apb_data = {
+	.gate = HW_SW_GATE_AUTO(0x0474, 16, 0, 1),
+};
+
 static struct peri_clk_data bsc1_data = {
 	.gate		= HW_SW_GATE(0x0458, 18, 2, 3),
 	.clocks		= CLOCKS("ref_crystal",
@@ -232,12 +290,26 @@ static struct ccu_data slave_ccu_data = {
 		.control	= CCU_POLICY_CTL(0x000c, 0, 1, 2),
 	},
 	.kona_clks	= {
+		[BCM21664_SLAVE_CCU_UARTB_APB] =
+			KONA_CLK(slave, uartb_apb, bus),
+		[BCM21664_SLAVE_CCU_UARTB2_APB] =
+			KONA_CLK(slave, uartb2_apb, bus),
+		[BCM21664_SLAVE_CCU_UARTB3_APB] =
+			KONA_CLK(slave, uartb3_apb, bus),
 		[BCM21664_SLAVE_CCU_UARTB] =
 			KONA_CLK(slave, uartb, peri),
 		[BCM21664_SLAVE_CCU_UARTB2] =
 			KONA_CLK(slave, uartb2, peri),
 		[BCM21664_SLAVE_CCU_UARTB3] =
 			KONA_CLK(slave, uartb3, peri),
+		[BCM21664_SLAVE_CCU_BSC1_APB] =
+			KONA_CLK(slave, bsc1_apb, bus),
+		[BCM21664_SLAVE_CCU_BSC2_APB] =
+			KONA_CLK(slave, bsc2_apb, bus),
+		[BCM21664_SLAVE_CCU_BSC3_APB] =
+			KONA_CLK(slave, bsc3_apb, bus),
+		[BCM21664_SLAVE_CCU_BSC4_APB] =
+			KONA_CLK(slave, bsc4_apb, bus),
 		[BCM21664_SLAVE_CCU_BSC1] =
 			KONA_CLK(slave, bsc1, peri),
 		[BCM21664_SLAVE_CCU_BSC2] =