-
Notifications
You must be signed in to change notification settings - Fork 61
/
Aarch64LIRAssembler.java
1923 lines (1802 loc) · 77.1 KB
/
Aarch64LIRAssembler.java
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*
* Copyright (c) 2017-2018, APT Group, School of Computer Science,
* The University of Manchester. All rights reserved.
* Copyright (c) 2009, 2011, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* version 2 for more details (a copy is included in the LICENSE file that
* accompanied this code).
*
* You should have received a copy of the GNU General Public License version
* 2 along with this work; if not, write to the Free Software Foundation,
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
*/
package com.sun.c1x.target.aarch64;
import static com.sun.cri.ci.CiCallingConvention.Type.*;
import static com.sun.cri.ci.CiValue.*;
import java.util.*;
import com.oracle.max.asm.*;
import com.oracle.max.asm.target.aarch64.*;
import com.oracle.max.asm.target.aarch64.Aarch64Assembler.*;
import com.oracle.max.criutils.*;
import com.sun.c1x.*;
import com.sun.c1x.asm.*;
import com.sun.c1x.gen.LIRGenerator.*;
import com.sun.c1x.ir.*;
import com.sun.c1x.lir.*;
import com.sun.c1x.lir.FrameMap.*;
import com.sun.c1x.stub.*;
import com.sun.c1x.util.*;
import com.sun.cri.ci.*;
import com.sun.cri.ci.CiTargetMethod.*;
import com.sun.cri.xir.*;
import com.sun.cri.xir.CiXirAssembler.*;
import com.sun.max.platform.*;
import com.sun.max.unsafe.Word;
import com.sun.max.vm.compiler.*;
public final class Aarch64LIRAssembler extends LIRAssembler {
private static final Object[] NO_PARAMS = new Object[0];
private static final CiRegister SHIFTCount = Aarch64.r1;
private static final long DoubleSignMask = 0x7FFFFFFFFFFFFFFFL;
final CiTarget target;
final Aarch64MacroAssembler masm;
final CiRegister scratchRegister;
public Aarch64LIRAssembler(C1XCompilation compilation, TargetMethodAssembler tasm) {
super(compilation, tasm);
masm = (Aarch64MacroAssembler) tasm.asm;
target = compilation.target;
scratchRegister = compilation.registerConfig.getScratchRegister();
}
private CiAddress asAddress(CiValue value) {
if (value.isAddress()) {
return (CiAddress) value;
}
assert value.isStackSlot();
return compilation.frameMap().toStackAddress((CiStackSlot) value);
}
@Override
protected void emitOsrEntry() {
if (true) {
throw Util.unimplemented();
}
}
@Override
protected int initialFrameSizeInBytes() {
return frameMap.frameSize();
}
@Override
protected void emitReturn(CiValue result) {
// TODO: Consider adding safepoint polling at return!
masm.ret();
}
@Override
protected void emitInfopoint(CiValue dst, LIRDebugInfo info, Infopoint.Op op) {
switch (op) {
case HERE:
tasm.recordSafepoint(codePos(), info);
masm.adr(dst.asRegister(), 0);
break;
case UNCOMMON_TRAP:
directCall(CiRuntimeCall.Deoptimize, info);
break;
case INFO:
tasm.recordSafepoint(codePos(), info);
break;
default:
throw Util.shouldNotReachHere();
}
}
@Override
protected void emitMonitorAddress(int monitor, CiValue dst) {
CiStackSlot slot = frameMap.toMonitorBaseStackAddress(monitor);
masm.leaq(dst.asRegister(), new CiAddress(slot.kind, Aarch64.sp.asValue(), slot.index() * target.arch.wordSize));
}
@Override
protected void emitPause() {
masm.pause();
}
@Override
protected void emitBreakpoint() {
masm.brk();
}
@Override
protected void emitIfBit(CiValue address, CiValue bitNo) {
assert false : "emitIfBit Aarch64IRAssembler";
masm.crashme();
masm.insertForeverLoop();
}
@Override
protected void emitStackAllocate(StackBlock stackBlock, CiValue dst) {
masm.leaq(dst.asRegister(), compilation.frameMap().toStackAddress(stackBlock));
}
private void moveRegs(CiRegister fromReg, CiRegister toReg) {
if (fromReg != toReg) {
masm.mov(64, toReg, fromReg);
}
}
@Override
public void emitTraps() {
for (int i = 0; i < C1XOptions.MethodEndBreakpointGuards; ++i) {
masm.brk();
}
masm.nop(8);
}
private void const2reg(CiRegister dst, float constant) {
masm.mov(scratchRegister, Float.floatToRawIntBits(constant));
masm.fmov(32, dst, scratchRegister);
}
private void const2reg(CiRegister dst, double constant) {
masm.mov(scratchRegister, Double.doubleToRawLongBits(constant));
masm.fmov(64, dst, scratchRegister);
}
@Override
protected void const2reg(CiValue src, CiValue dest, LIRDebugInfo info) {
assert src.isConstant();
assert dest.isRegister();
CiConstant c = (CiConstant) src;
// Checkstyle: off
switch (c.kind) {
case Boolean:
case Byte:
case Char:
case Short:
case Jsr:
case Int:
masm.mov(dest.asRegister(), c.asInt());
break;
case Long:
masm.mov(dest.asRegister(), c.asLong());
break;
case Object:
movoop(dest.asRegister(), c);
break;
case Float:
const2reg(dest.asRegister(), c.asFloat());
break;
case Double:
const2reg(dest.asRegister(), c.asDouble());
break;
default:
throw Util.shouldNotReachHere();
}
// Checkstyle: on
}
private CiKind setScratchRegister(CiConstant constant) {
CiKind kind = CiKind.Int;
switch (constant.kind) {
case Boolean:
case Byte:
masm.movz(64, scratchRegister, constant.asInt() & 0xFF, 0);
break;
case Char:
case Short:
masm.movz(64, scratchRegister, constant.asInt() & 0xFFFF, 0);
break;
case Jsr:
case Int:
masm.mov(scratchRegister, constant.asInt());
break;
case Float:
masm.mov(scratchRegister, Float.floatToRawIntBits(constant.asFloat()));
break;
case Object:
movoop(scratchRegister, constant);
kind = CiKind.Long;
break;
case Long:
masm.mov(scratchRegister, constant.asLong());
kind = CiKind.Long;
break;
case Double:
masm.mov(scratchRegister, Double.doubleToRawLongBits(constant.asDouble()));
kind = CiKind.Long;
break;
default:
throw Util.shouldNotReachHere("Unknown constant kind for const2stack: " + constant.kind);
}
return kind;
}
@Override
protected void const2stack(CiValue src, CiValue dst) {
assert src.isConstant();
assert dst.isStackSlot();
CiStackSlot slot = (CiStackSlot) dst;
CiConstant c = (CiConstant) src;
CiAddress address = frameMap.toStackAddress(slot);
CiKind kind = setScratchRegister(c);
masm.store(scratchRegister, address, kind);
}
@Override
protected void const2mem(CiValue src, CiValue dst, CiKind kind, LIRDebugInfo info) {
assert src.isConstant();
assert dst.isAddress();
CiConstant constant = (CiConstant) src;
CiAddress addr = asAddress(dst);
CiKind storeKind = setScratchRegister(constant);
masm.store(scratchRegister, addr, storeKind);
if (info != null) {
tasm.recordImplicitException(codePos() - 4, info);
}
}
@Override
protected void reg2reg(CiValue src, CiValue dest) {
assert src.isRegister();
assert dest.isRegister();
if (dest.kind.isFloat()) {
masm.fmov(32, dest.asRegister(), src.asRegister());
} else if (dest.kind.isDouble()) {
masm.fmov(64, dest.asRegister(), src.asRegister());
} else {
moveRegs(src.asRegister(), dest.asRegister());
}
}
@Override
protected void reg2stack(CiValue src, CiValue dst, CiKind kind) {
assert src.isRegister();
assert dst.isStackSlot();
CiAddress addr = frameMap.toStackAddress((CiStackSlot) dst);
masm.store(src.asRegister(), addr, src.kind.stackKind());
}
@Override
protected void reg2mem(CiValue src, CiValue dest, CiKind kind, LIRDebugInfo info, boolean unaligned) {
CiAddress destAddress = (CiAddress) dest;
masm.store(src.asRegister(), destAddress, kind);
if (info != null) {
tasm.recordImplicitException(codePos() - 4, info);
}
}
@Override
protected void stack2reg(CiValue src, CiValue dest, CiKind kind) {
assert src.isStackSlot();
assert dest.isRegister();
CiAddress addr = frameMap.toStackAddress((CiStackSlot) src);
masm.load(dest.asRegister(), addr, dest.kind.stackKind());
}
@Override
protected void mem2mem(CiValue src, CiValue dest, CiKind kind) {
masm.load(masm.scratchRegister, (CiAddress) src, kind);
masm.store(masm.scratchRegister, (CiAddress) dest, kind);
}
@Override
protected void mem2stack(CiValue src, CiValue dest, CiKind kind) {
assert false : "mem2stack not implemented";
}
@Override
protected void stack2stack(CiValue src, CiValue dest, CiKind kind) {
masm.load(scratchRegister, frameMap.toStackAddress((CiStackSlot) src), src.kind);
masm.store(scratchRegister, frameMap.toStackAddress((CiStackSlot) dest), src.kind);
}
@Override
protected void mem2reg(CiValue src, CiValue dest, CiKind kind, LIRDebugInfo info, boolean unaligned) {
assert src.isAddress();
assert dest.isRegister() : "dest=" + dest;
CiAddress addr = (CiAddress) src;
masm.load(dest.asRegister(), addr, kind);
if (info != null) {
tasm.recordImplicitException(codePos() - 4, info);
}
}
@Override
protected void emitReadPrefetch(CiValue src) {
assert false : "emitReadPrefetch unimplemented!";
}
@Override
protected void emitOp3(LIROp3 op) {
// Checkstyle: off
switch (op.code) {
case Idiv:
case Irem:
arithmeticDiv(32, op.code, op.opr1(), op.opr2(), op.result(), op.info);
break;
case Iudiv:
case Iurem:
arithmeticUdiv(32, op.code, op.opr1(), op.opr2(), op.result(), op.info);
break;
case Ldiv:
case Lrem:
arithmeticDiv(64, op.code, op.opr1(), op.opr2(), op.result(), op.info);
break;
case Ludiv:
case Lurem:
arithmeticUdiv(64, op.code, op.opr1(), op.opr2(), op.result(), op.info);
break;
default:
throw Util.shouldNotReachHere();
}
// Checkstyle: on
}
private boolean assertEmitBranch(LIRBranch op) {
assert op.block() == null || op.block().label() == op.label() : "wrong label";
if (op.block() != null) {
branchTargetBlocks.add(op.block());
}
if (op.unorderedBlock() != null) {
branchTargetBlocks.add(op.unorderedBlock());
}
return true;
}
private boolean assertEmitTableSwitch(LIRTableSwitch op) {
assert op.defaultTarget != null;
branchTargetBlocks.add(op.defaultTarget);
for (BlockBegin target : op.targets) {
assert target != null;
branchTargetBlocks.add(target);
}
return true;
}
@Override
protected void emitTableSwitch(LIRTableSwitch op) {
assert assertEmitTableSwitch(op);
CiRegister value = op.value().asRegister();
final Buffer buf = masm.codeBuffer;
// Compare index against jump table bounds
int highKey = op.lowKey + op.targets.length - 1;
if (op.lowKey != 0) {
// subtract the low value from the switch value
masm.sub(64, value, value, (long) op.lowKey);
masm.cmp(64, value, highKey - op.lowKey);
} else {
masm.cmp(64, value, highKey);
}
// Jump to default target if index is not within the jump table
masm.branchConditionally(ConditionFlag.HI, op.defaultTarget.label());
// Set scratch to address of jump table
int adrPos = buf.position();
masm.adr(scratchRegister, 0);
// Load jump table entry into value and jump to it
masm.add(64, value, scratchRegister, value, ShiftType.LSL, 2); // Shift left by 2 to make offset in bytes
masm.jmp(value);
// Inserting padding so that jump table address is 4-byte aligned
if ((buf.position() & 0x3) != 0) {
masm.nop(4 - (buf.position() & 0x3));
}
// Patch setUpScratch instructions above now that we know the position of the jump table
int jumpTablePos = buf.position();
buf.setPosition(adrPos);
masm.adr(scratchRegister, jumpTablePos - adrPos);
buf.setPosition(jumpTablePos);
// Emit jump table entries
for (BlockBegin target : op.targets) {
Label label = target.label();
if (label.isBound()) {
int imm32 = label.position() - jumpTablePos;
buf.emitInt(imm32);
} else {
label.addPatchAt(buf.position());
buf.emitByte(PatchLabelKind.TABLE_SWITCH.encoding);
buf.emitByte(0);
buf.emitShort(0);
}
}
JumpTable jt = new JumpTable(jumpTablePos, op.lowKey, highKey, 4);
tasm.targetMethod.addAnnotation(jt);
}
@Override
protected void emitBranch(LIRBranch op) {
assert assertEmitBranch(op);
if (op.cond() == Condition.TRUE) {
masm.b(op.label());
if (op.info != null) {
tasm.recordImplicitException(codePos() - 4, op.info); // ADDED EXCEPTION
}
} else {
ConditionFlag acond;
if (op.code == LIROpcode.CondFloatBranch) {
assert op.unorderedBlock() != null : "must have unordered successor";
masm.branchConditionally(ConditionFlag.VS, op.unorderedBlock().label());
switch (op.cond()) {
case EQ:
acond = ConditionFlag.EQ;
break;
case NE:
acond = ConditionFlag.NE;
break;
case LT:
acond = ConditionFlag.LO;
break;
case LE:
acond = ConditionFlag.LS;
break;
case GE:
acond = ConditionFlag.GE;
break;
case GT:
acond = ConditionFlag.GT;
break;
default:
throw Util.shouldNotReachHere();
}
} else {
acond = convertCondition(op.cond());
}
masm.branchConditionally(acond, op.label());
}
}
@Override
protected void emitConvert(LIRConvert op) {
CiValue src = op.operand();
CiValue dest = op.result();
switch (op.opcode) {
case I2L:
masm.sxt(64, 32, dest.asRegister(), src.asRegister());
break;
case L2I:
masm.and(64, dest.asRegister(), src.asRegister(), 0xFFFFFFFFL);
break;
case I2B:
masm.and(64, dest.asRegister(), src.asRegister(), 0xFFL);
masm.sxt(64, 8, dest.asRegister(), src.asRegister());
break;
case I2C:
masm.and(64, dest.asRegister(), src.asRegister(), 0xFFFFL);
break;
case I2S:
masm.and(64, dest.asRegister(), src.asRegister(), 0xFFFFL);
masm.sxt(64, 16, dest.asRegister(), src.asRegister());
break;
case F2D:
masm.fcvt(32, dest.asRegister(), src.asRegister());
break;
case D2F:
masm.fcvt(64, dest.asRegister(), src.asRegister());
break;
case I2F:
masm.scvtf(32, 32, dest.asRegister(), src.asRegister());
break;
case I2D:
masm.scvtf(64, 32, dest.asRegister(), src.asRegister());
break;
case F2I:
masm.fcvtzs(32, 32, dest.asRegister(), src.asRegister());
break;
case D2I:
masm.fcvtzs(32, 64, dest.asRegister(), src.asRegister());
break;
case L2F:
masm.scvtf(32, 64, dest.asRegister(), src.asRegister());
break;
case L2D:
masm.scvtf(64, 64, dest.asRegister(), src.asRegister());
break;
case F2L:
masm.fcvtzs(64, 32, dest.asRegister(), src.asRegister());
break;
case D2L:
masm.fcvtzs(64, 64, dest.asRegister(), src.asRegister());
break;
case MOV_I2F:
masm.fmovCpu2Fpu(32, dest.asRegister(), src.asRegister());
break;
case MOV_L2D:
masm.fmovCpu2Fpu(64, dest.asRegister(), src.asRegister());
break;
case MOV_F2I:
masm.fmovFpu2Cpu(32, dest.asRegister(), src.asRegister());
break;
case MOV_D2L:
masm.fmovFpu2Cpu(64, dest.asRegister(), src.asRegister());
break;
default:
throw Util.shouldNotReachHere();
}
}
@Override
protected void emitCompareAndSwap(LIRCompareAndSwap op) {
Aarch64Address address = Aarch64Address.createBaseRegisterOnlyAddress(op.address().asRegister());
CiRegister newval = op.newValue().asRegister();
CiRegister cmpval = op.expectedValue().asRegister();
assert newval != null : "new val must be register";
assert cmpval != newval : "cmp and new values must be in different registers";
assert cmpval != address.base() : "cmp and addr must be in different registers";
assert newval != address.base() : "new value and addr must be in different registers";
assert cmpval != address.index() : "cmp and addr must be in different registers";
assert newval != address.index() : "new value and addr must be in different registers";
if (op.code == LIROpcode.CasInt) {
masm.cas(32, newval, cmpval, address);
} else {
assert op.code == LIROpcode.CasLong || op.code == LIROpcode.CasObj;
masm.cas(64, newval, cmpval, address);
}
}
@Override
protected void emitConditionalMove(Condition condition, CiValue opr1, CiValue opr2, CiValue result) {
ConditionFlag acond;
ConditionFlag ncond;
switch (condition) {
case EQ:
acond = ConditionFlag.EQ;
ncond = ConditionFlag.NE;
break;
case NE:
ncond = ConditionFlag.EQ;
acond = ConditionFlag.NE;
break;
case LT:
acond = ConditionFlag.LT;
ncond = ConditionFlag.GE;
break;
case LE:
acond = ConditionFlag.LE;
ncond = ConditionFlag.GT;
break;
case GE:
acond = ConditionFlag.GE;
ncond = ConditionFlag.LT;
break;
case GT:
acond = ConditionFlag.GT;
ncond = ConditionFlag.LE;
break;
case BE:
acond = ConditionFlag.LS;
ncond = ConditionFlag.HI;
break;
case BT:
acond = ConditionFlag.LO;
ncond = ConditionFlag.HS;
break;
case AE:
acond = ConditionFlag.HS;
ncond = ConditionFlag.LO;
break;
case AT:
acond = ConditionFlag.HI;
ncond = ConditionFlag.LS;
break;
default:
throw Util.shouldNotReachHere();
}
CiValue def = opr1; // assume left operand as default
CiValue other = opr2;
if (opr2.isRegister() && opr2.asRegister() == result.asRegister()) {
// if the right operand is already in the result register, then use it as the default
def = opr2;
other = opr1;
// and flip the condition
ConditionFlag tcond = acond;
acond = ncond;
ncond = tcond;
}
if (def.isRegister()) {
reg2reg(def, result);
} else if (def.isStackSlot()) {
stack2reg(def, result, result.kind);
} else {
assert def.isConstant();
const2reg(def, result, null);
}
if (!other.isConstant()) {
// optimized version that does not require a branch
if (other.isRegister()) {
assert other.asRegister() != result.asRegister() : "other already overwritten by previous move";
if (other.kind.isInt()) {
masm.cmov(32, result.asRegister(), other.asRegister(), result.asRegister(), ncond);
} else {
masm.cmov(64, result.asRegister(), other.asRegister(), result.asRegister(), ncond);
}
} else {
assert other.isStackSlot();
CiStackSlot otherSlot = (CiStackSlot) other;
masm.load(scratchRegister, frameMap.toStackAddress(otherSlot), other.kind);
masm.cmov(64, result.asRegister(), scratchRegister, result.asRegister(), ncond);
}
} else {
// conditional move not available, use emit a branch and move
Label skip = new Label();
masm.branchConditionally(acond, skip);
if (other.isRegister()) {
reg2reg(other, result);
} else if (other.isStackSlot()) {
stack2reg(other, result, result.kind);
} else {
assert other.isConstant();
const2reg(other, result, null);
}
masm.bind(skip);
}
}
@Override
protected void emitArithOp(LIROpcode code, CiValue left, CiValue right, CiValue dest, LIRDebugInfo info) {
assert info == null : "should never be used : idiv/irem and ldiv/lrem not handled by this method";
assert Util.archKindsEqual(left.kind, right.kind) || (left.kind == CiKind.Long && right.kind == CiKind.Int)
: code.toString() + " left arch is " + left.kind + " and right arch is " + right.kind;
assert left.equals(dest) : "left and dest must be equal";
CiKind kind = left.kind;
if (left.isRegister()) {
final int size = kind.isInt() || kind.isFloat() ? 32 : 64;
CiRegister lreg = left.asRegister();
CiRegister rreg;
if (right.isConstant() && (kind.isInt() || kind.isLong())) {
assert kind.isInt() || kind.isLong();
final long delta = ((CiConstant) right).asLong();
switch (code) {
case Add:
masm.add(size, dest.asRegister(), lreg, delta);
break;
case Sub:
masm.sub(size, dest.asRegister(), lreg, delta);
break;
default:
throw Util.shouldNotReachHere();
}
return;
}
if (right.isRegister()) {
rreg = right.asRegister();
} else if (right.isStackSlot()) {
CiAddress raddr = frameMap.toStackAddress((CiStackSlot) right);
if (kind.isInt() || kind.isLong()) {
masm.load(scratchRegister, raddr, kind);
rreg = scratchRegister;
} else {
assert kind.isFloat() || kind.isDouble();
masm.load(Aarch64.d30, raddr, kind);
rreg = Aarch64.d30;
}
} else {
assert right.isConstant();
assert kind.isFloat() || kind.isDouble();
if (kind.isFloat()) {
tasm.recordDataReferenceInCode(CiConstant.forFloat(((CiConstant) right).asFloat()));
} else {
tasm.recordDataReferenceInCode(CiConstant.forDouble(((CiConstant) right).asDouble()));
}
masm.adr(scratchRegister, 0); // this gets patched by Aarch64InstructionDecoder.patchRelativeInstruction
masm.nop(Aarch64MacroAssembler.PLACEHOLDER_INSTRUCTIONS_FOR_LONG_OFFSETS);
rreg = Aarch64.d30;
masm.load(rreg, Aarch64Address.createBaseRegisterOnlyAddress(scratchRegister), kind);
}
if (kind.isInt() || kind.isLong()) {
switch (code) {
case Add:
masm.add(size, dest.asRegister(), lreg, rreg);
break;
case Sub:
masm.sub(size, dest.asRegister(), lreg, rreg);
break;
case Mul:
masm.mul(size, dest.asRegister(), lreg, rreg);
break;
case Rem:
masm.rem(size, dest.asRegister(), lreg, rreg);
break;
default:
throw Util.shouldNotReachHere();
}
} else {
assert kind.isFloat() || kind.isDouble();
assert rreg.isFpu() : "must be floating point register";
switch (code) {
case Add:
masm.fadd(size, dest.asRegister(), lreg, rreg);
break;
case Sub:
masm.fsub(size, dest.asRegister(), lreg, rreg);
break;
case Mul:
masm.fmul(size, dest.asRegister(), lreg, rreg);
break;
case Div:
masm.fdiv(size, dest.asRegister(), lreg, rreg);
break;
case Rem:
masm.frem(size, dest.asRegister(), lreg, rreg);
break;
default:
throw Util.shouldNotReachHere();
}
}
} else {
assert kind.isInt();
CiAddress laddr = asAddress(left);
masm.load(scratchRegister, laddr, kind);
if (right.isRegister()) {
CiRegister rreg = right.asRegister();
switch (code) {
case Add:
masm.add(32, scratchRegister, scratchRegister, rreg);
break;
case Sub:
masm.sub(32, scratchRegister, scratchRegister, rreg);
break;
default:
throw Util.shouldNotReachHere();
}
} else {
assert right.isConstant();
int c = ((CiConstant) right).asInt();
switch (code) {
case Add:
masm.add(32, scratchRegister, scratchRegister, (long) c);
break;
case Sub:
masm.sub(32, scratchRegister, scratchRegister, (long) c);
break;
default:
throw Util.shouldNotReachHere();
}
}
masm.store(scratchRegister, laddr, kind);
}
}
@Override
protected void emitIntrinsicOp(LIROpcode code, CiValue value, CiValue unused, CiValue dest, LIROp2 op) {
assert value.kind.isDouble();
switch (code) {
case Abs:
masm.fabs(64, dest.asRegister(), value.asRegister());
break;
case Sqrt:
masm.fsqrt(64, dest.asRegister(), value.asRegister());
break;
default:
throw Util.shouldNotReachHere();
}
}
// TODO (fz): Optimize using logical immediates where possible
@Override
protected void emitLogicOp(LIROpcode code, CiValue left, CiValue right, CiValue dst) {
assert left.isRegister();
assert dst.isRegister();
int size = left.kind.isInt() ? 32 : 64;
CiRegister reg = left.asRegister();
CiRegister dest = dst.asRegister();
CiRegister rright;
if (right.isStackSlot()) {
// added support for stack operands
CiAddress raddr = frameMap.toStackAddress((CiStackSlot) right);
masm.load(scratchRegister, raddr, right.kind);
rright = scratchRegister;
} else if (right.isConstant()) {
if (left.kind.isInt()) {
int val = ((CiConstant) right).asInt();
masm.mov32BitConstant(scratchRegister, val);
} else {
long val = ((CiConstant) right).asLong();
masm.mov64BitConstant(scratchRegister, val);
}
rright = scratchRegister;
} else {
rright = right.asRegister();
}
switch (code) {
case LogicAnd:
masm.and(size, dest, reg, rright);
break;
case LogicOr:
masm.or(size, dest, reg, rright);
break;
case LogicXor:
masm.eor(size, dest, reg, rright);
break;
default:
throw Util.shouldNotReachHere();
}
}
void arithmeticDiv(int size, LIROpcode code, CiValue left, CiValue right, CiValue result, LIRDebugInfo info) {
assert left.isRegister() : "left must be register";
assert right.isRegister() || right.isConstant() : "right must be register or constant";
assert result.isRegister() : "result must be register";
assert size == 32 || size == 64 : "size must be 32 or 64";
CiRegister numerator = left.asRegister();
CiRegister quotient = result.asRegister();
if (right.isConstant()) {
Util.shouldNotReachHere("cwi: I assume this is dead code, notify me if I'm wrong...");
} else {
CiRegister denominator = right.asRegister();
Label continuation = new Label();
if (C1XOptions.GenSpecialDivChecks) {
// check for special case of MIN_VALUE / -1
Label normalCase = new Label();
masm.mov(scratchRegister, size == 32 ? Integer.MIN_VALUE : Long.MIN_VALUE);
masm.cmp(size, numerator, scratchRegister);
masm.branchConditionally(ConditionFlag.NE, normalCase);
masm.cmp(size, denominator, -1);
if (code == LIROpcode.Irem || code == LIROpcode.Lrem) {
// prepare scratch for possible special case where remainder = 0
masm.mov(quotient, 0);
}
masm.branchConditionally(ConditionFlag.EQ, continuation);
masm.bind(normalCase);
}
int offset = masm.insertDivByZeroCheck(size, denominator);
tasm.recordImplicitException(offset, info);
if (code == LIROpcode.Irem || code == LIROpcode.Lrem) {
if (quotient == numerator || quotient == denominator) {
quotient = scratchRegister;
}
masm.sdiv(size, quotient, numerator, denominator);
masm.msub(size, result.asRegister(), quotient, denominator, numerator);
} else {
assert code == LIROpcode.Idiv || code == LIROpcode.Ldiv;
masm.sdiv(size, quotient, numerator, denominator);
}
masm.bind(continuation);
}
}
void arithmeticUdiv(int size, LIROpcode code, CiValue left, CiValue right, CiValue result, LIRDebugInfo info) {
assert left.isRegister() : "left must be register";
assert right.isRegister() : "right must be register";
assert result.isRegister() : "result must be register";
assert size == 32 || size == 64 : "size must be 32 or 64";
CiRegister numerator = left.asRegister();
CiRegister quotient = result.asRegister();
CiRegister denominator = right.asRegister();
int offset = masm.insertDivByZeroCheck(size, denominator);
tasm.recordImplicitException(offset, info);
if (code == LIROpcode.Iurem || code == LIROpcode.Lurem) {
if (quotient == numerator || quotient == denominator) {
quotient = scratchRegister;
}
masm.udiv(size, quotient, numerator, denominator);
masm.msub(size, result.asRegister(), quotient, denominator, numerator);
} else {
assert code == LIROpcode.Iudiv || code == LIROpcode.Ludiv;
masm.udiv(size, quotient, numerator, denominator);
}
}
private ConditionFlag convertCondition(Condition condition) {
ConditionFlag acond;
switch (condition) {
case EQ:
acond = ConditionFlag.EQ;
break;
case NE:
acond = ConditionFlag.NE;
break;
case LT:
acond = ConditionFlag.LT;
break;
case LE:
acond = ConditionFlag.LE;
break;
case GE:
acond = ConditionFlag.GE;
break;
case GT:
acond = ConditionFlag.GT;
break;
case BE:
acond = ConditionFlag.LS;
break;
case AE:
acond = ConditionFlag.HS;
break;
case BT:
acond = ConditionFlag.LO;
break;
case AT:
acond = ConditionFlag.HI;
break;
default:
throw Util.shouldNotReachHere();
}
return acond;
}
@Override
@SuppressWarnings("fallthrough")
protected void emitCompare(Condition condition, CiValue opr1, CiValue opr2, LIROp2 op) {
// Checkstyle: off
assert Util.archKindsEqual(opr1.kind.stackKind(), opr2.kind.stackKind()) || (opr1.kind == CiKind.Long && opr2.kind == CiKind.Int) : "nonmatching stack kinds (" + condition + "): " +
opr1.kind.stackKind() + "==" + opr2.kind.stackKind();
CiValue oldOpr1 = opr1;
if (opr1.isConstant()) {
CiValue newOpr1 = compilation.registerConfig.getScratchRegister().asValue(opr1.kind);
const2reg(opr1, newOpr1, null);
opr1 = newOpr1;
assert (opr1.kind != CiKind.Float);
assert (opr1.kind != CiKind.Long);
assert (opr1.kind != CiKind.Double);
}
if (opr1.isRegister()) {
CiRegister reg1 = opr1.asRegister();
if (opr2.isRegister()) {
// register - register
switch (opr1.kind) {
case Boolean:
case Byte:
case Char:
case Short:
case Int:
masm.cmp(32, reg1, opr2.asRegister());
break;
case Object:
case Long:
assert (reg1 != Aarch64.r16);
masm.cmp(64, reg1, opr2.asRegister());
break;
case Float:
masm.ucomisd(32, reg1, opr2.asRegister(), opr1.kind, opr2.kind);
break;
case Double:
masm.ucomisd(64, reg1, opr2.asRegister(), opr1.kind, opr2.kind);
break;
default:
throw Util.shouldNotReachHere(opr1.kind.toString());
}
} else if (opr2.isStackSlot()) {
// register - stack
CiStackSlot opr2Slot = (CiStackSlot) opr2;
switch (opr1.kind) {
case Boolean:
case Byte:
case Char: