FPGAA_Code

Note: Some of the code below is not created by me, I just store them in this repository. If you want to use these codes, plz contact me.

Codes

No	File	Functionality	Demo
1.	SEG7_LUT_6.v	/mod/ 6 7-segment display module.
2.	signed4bits_2funCal_disAddSub.v	/top/ 4 bits calculator can display, add, subtract numbers.
3.	signed4bits_3funCal_disAddSubMul.v	/top/ 4 bits calculator can display, add, subtract, multiply numbers.
4.	signed4bits_3funCal_disAddSubDiv.v	/top/ 4 bits calculator can display, add, subtract, divide numbers.
5.	signed4bits_4funCal_addSubMulDiv.v	/top/ 4 bits calculator can add, subtract, multiply, divide numbers.	YouTube
6.	button_counter_main.v	/top/ Display two sets of numbers as counters individually controlled by buttons and switch. (File gone~)
7.	COUNTER_BUTTON.v	/mod/ Control buttons and switchs to display counter values. With repeating adding bug.	YouTube
8.	COUNTER_DEBOUNCE.v	/mod/ Control buttons and switchs to display counter values. No bug.	YouTube
9.	counter_v1.v	/top/ Counter by 10.
10.	counter_tb_v1.v	/sim/ Testing file of counter_10.v.
11.	counter_v2.v	/top/ Counter with frequency divider by 5.
12.	counter_tb_v2.v	/sim/ Testing file of counter_tb_v2.v.
13.	counter_v3.v	/top/ Counter with frequency divider by 10.
14.	counter_tb_v3.v	/sim/ Testing file of counter_tb_v3.v.
15.	counter_v4.v	/top/ Counter with frequency divider by 10 with dislocation.
16.	counter_tb_v4.v	/sim/ Testing file of counter_tb_v4.v.
17.	counter_v5.v	/top/ Counter with frequency divider by 50x10.
18.	counter_v5_10.v	/mod/ Counter with frequency divider by 10 with dislocation.
19.	counter_v5_50.v	/mod/ Counter with frequency divider by 50 with dislocation.
20.	counter_tb_v5.v	/sim/ Testing file of counter_tb_v5.v.
21.	counter_v6.v	/top/ Counter with frequency divider by 10x10.
22.	counter_tb_v6.v	/sim/ Testing file of counter_tb_v6.v.
23.	counter_v7_24hClock.v	/top/ Display counter output as 24h digital clock to 7-segment LED.
24.	counter_v7.v	/top/ Counter with frequency divider by 24x60x60.
25.	counter_v7_24.v	/mod/ Counter with frequency divider by 24 with dislocation.
26.	counter_v7_60.v	/mod/ Counter with frequency divider by 60 with dislocation.
27.	counter_tb_v7.v	/sim/ Testing file of counter_tb_v7.v.
28.	DE10_LITE_BUTTON_COUNTER.v	/top/ Apply "counter_v7.v" to 7-segment LED.	YouTube
29.	Shot_the_Clock.v	/top/ Display 24h clock with a button to shot out light turning 7-segment off one by one.	YouTube
30.	clock_all.v	/mod/ Generate 10 based clock from internal clocks.
31.	eclock.v	/mod/ Generate 24h clock signal, receive and change signal output when triggered with signal.
32.	ledMeteor.v	/mod/ Light up ten on-board LED light as meteor light when triggered with signal.
33.	SW_debounce.v	/mod/ Generated debounced switch signal.
34.	dataRegister8_9-1.qar	/arc/ Data register.
35.	dataRegister8_9-2.qar	/arc/ Data register with output.
36.	dataRegister8_9-3.qar	/arc/ Data register with I/O system.
37.	dataRegister8_9-4.qar	/arc/ Data register with I/O System with defined initial state.
38.	dataRegister8_9-5.qar	/arc/ ALU.
39.	dataRegister8_10-1.qar	/arc/ ROM
40.	dataRegister8_10-2.qar	/arc/ Data direct system.
41.	dataRegister8_10-3.qar	/arc/ Write address control system.
42.	data_v.qar	/arc/ Full pipeline CPU data pipeline.
43.	dataRegister8_11.qar	/arc/ Additional parts of pipeline CPU.
44.	cpu_v_ex13.qar	/arc/ Full pipeline CPU design with LEDs lighting code (ex12), logic analyzer, and customized 7-segments lighting code.
45.	StateMachine_shot_the_clock.qar	/arc/ Use state machine to control laser firing machanism of midterm project.	YouTube

Note

1. The divider function in No.4 & No.5 can't properly calculate the quotient of $Z^+\div Z^-$. Not sure about $Z^-\div Z^-$.
2. Code in No.23 can't display properly since the FPGA's base clock is several hundred megahertz, and each second is based on each clock cycle.

Final

Modify the midterm project to operate with CPU and State Machine.