Skip to content

Commit

Permalink
Renamed REG_* fields to NDR_*, so that we don't conflict with _GNU_SO…
Browse files Browse the repository at this point in the history 
…URCES.
  • Loading branch information
@vlutas
vlutas committed Jul 29, 2020
1 parent 02b7177 commit 144baa5
Show file tree
Hide file tree
Showing 10 changed files with 1,115 additions and 1,115 deletions.
176 changes: 88 additions & 88 deletions bddisasm/bddisasm.c
View file

Large diffs are not rendered by default.

1,448 changes: 724 additions & 724 deletions bddisasm/include/instructions.h
View file

Large diffs are not rendered by default.

222 changes: 111 additions & 111 deletions bdshemu/bdshemu.c
View file

Large diffs are not rendered by default.

4 changes: 2 additions & 2 deletions disasmtool/disasmtool.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -34,7 +34,7 @@ typedef struct _DISASM_OPTIONS
uint8_t Ring; // Ring - 0, 1, 2 or 3.
uint8_t Vendor; // Proffered vendor.
char *FileName; // Input file, if any.
size_t ShemuRegs[REG_R15 + 1];
size_t ShemuRegs[NDR_R15 + 1];
BOOLEAN UseShemuRegs;
} DISASM_OPTIONS, *PDISASM_OPTIONS;

Expand Down Expand Up @@ -1439,7 +1439,7 @@ handle_shemu(
ctx.Registers.RegRsp = 0x101000;
ctx.IntbufSize = (DWORD)shellSize + STACK_SIZE;

ctx.Registers.RegFlags = REG_RFLAG_IF | 2;
ctx.Registers.RegFlags = NDR_RFLAG_IF | 2;
ctx.Registers.RegRip = ctx.ShellcodeBase + offset;

ctx.Segments.Cs.Selector = 0x10;
Expand Down
48 changes: 24 additions & 24 deletions disasmtool_lix/dumpers.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1764,36 +1764,36 @@ std::string reg_to_str(const int reg, const ND_REG_TYPE type)

case ND_REG_GPR:
switch (reg) {
case REG_RAX: return "rax";
case REG_RCX: return "rcx";
case REG_RDX: return "rdx";
case REG_RBX: return "rbx";
case REG_RSP: return "rsp";
case REG_RBP: return "rbp";
case REG_RSI: return "rsi";
case REG_RDI: return "rdi";
case REG_R8: return "r8";
case REG_R9: return "r9";
case REG_R10: return "r10";
case REG_R11: return "r11";
case REG_R12: return "r12";
case REG_R13: return "r13";
case REG_R14: return "r14";
case REG_R15: return "r15";
case NDR_RAX: return "rax";
case NDR_RCX: return "rcx";
case NDR_RDX: return "rdx";
case NDR_RBX: return "rbx";
case NDR_RSP: return "rsp";
case NDR_RBP: return "rbp";
case NDR_RSI: return "rsi";
case NDR_RDI: return "rdi";
case NDR_R8: return "r8";
case NDR_R9: return "r9";
case NDR_R10: return "r10";
case NDR_R11: return "r11";
case NDR_R12: return "r12";
case NDR_R13: return "r13";
case NDR_R14: return "r14";
case NDR_R15: return "r15";
}

return "<u>";

case ND_REG_SEG:
switch (reg) {
case REG_ES: return "es";
case REG_CS: return "cs";
case REG_SS: return "ss";
case REG_DS: return "ds";
case REG_FS: return "fs";
case REG_GS: return "gs";
case REG_INV6: return "inv6";
case REG_INV7: return "inv7";
case NDR_ES: return "es";
case NDR_CS: return "cs";
case NDR_SS: return "ss";
case NDR_DS: return "ds";
case NDR_FS: return "fs";
case NDR_GS: return "gs";
case NDR_INV6: return "inv6";
case NDR_INV7: return "inv7";
}

return "<u>";
Expand Down
194 changes: 97 additions & 97 deletions inc/cpuidflags.h
View file

Large diffs are not rendered by default.

126 changes: 63 additions & 63 deletions inc/registers.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -10,139 +10,139 @@
//
enum
{
REG_RAX, REG_RCX, REG_RDX, REG_RBX, REG_RSP, REG_RBP, REG_RSI, REG_RDI,
REG_R8, REG_R9, REG_R10, REG_R11, REG_R12, REG_R13, REG_R14, REG_R15,
NDR_RAX, NDR_RCX, NDR_RDX, NDR_RBX, NDR_RSP, NDR_RBP, NDR_RSI, NDR_RDI,
NDR_R8, NDR_R9, NDR_R10, NDR_R11, NDR_R12, NDR_R13, NDR_R14, NDR_R15,
};

enum
{
REG_EAX, REG_ECX, REG_EDX, REG_EBX, REG_ESP, REG_EBP, REG_ESI, REG_EDI,
REG_R8D, REG_R9D, REG_R10D,REG_R11D,REG_R12D,REG_R13D,REG_R14D,REG_R15D,
NDR_EAX, NDR_ECX, NDR_EDX, NDR_EBX, NDR_ESP, NDR_EBP, NDR_ESI, NDR_EDI,
NDR_R8D, NDR_R9D, NDR_R10D,NDR_R11D,NDR_R12D,NDR_R13D,NDR_R14D,NDR_R15D,
};

enum
{
REG_AX, REG_CX, REG_DX, REG_BX, REG_SP, REG_BP, REG_SI, REG_DI,
REG_R8W, REG_R9W, REG_R10W,REG_R11W,REG_R12W,REG_R13W,REG_R14W,REG_R15W,
NDR_AX, NDR_CX, NDR_DX, NDR_BX, NDR_SP, NDR_BP, NDR_SI, NDR_DI,
NDR_R8W, NDR_R9W, NDR_R10W,NDR_R11W,NDR_R12W,NDR_R13W,NDR_R14W,NDR_R15W,
};

enum
{
REG_AL, REG_CL, REG_DL, REG_BL, REG_AH, REG_CH, REG_DH, REG_BH,
NDR_AL, NDR_CL, NDR_DL, NDR_BL, NDR_AH, NDR_CH, NDR_DH, NDR_BH,
};

enum
{
REG_AL64, REG_CL64, REG_DL64, REG_BL64, REG_SPL, REG_BPL, REG_SIL, REG_DIL,
REG_R8L, REG_R9L, REG_R10L, REG_R11L, REG_R12L, REG_R13L, REG_R14L, REG_R15L,
NDR_AL64, NDR_CL64, NDR_DL64, NDR_BL64, NDR_SPL, NDR_BPL, NDR_SIL, NDR_DIL,
NDR_R8L, NDR_R9L, NDR_R10L, NDR_R11L, NDR_R12L, NDR_R13L, NDR_R14L, NDR_R15L,
};

enum
{
REG_ES, REG_CS, REG_SS, REG_DS, REG_FS, REG_GS, REG_INV6, REG_INV7,
NDR_ES, NDR_CS, NDR_SS, NDR_DS, NDR_FS, NDR_GS, NDR_INV6, NDR_INV7,
};

enum
{
REG_CR0, REG_CR1, REG_CR2, REG_CR3, REG_CR4, REG_CR5, REG_CR6, REG_CR7,
REG_CR8, REG_CR9, REG_CR10, REG_CR11, REG_CR12, REG_CR13, REG_CR14, REG_CR15,
NDR_CR0, NDR_CR1, NDR_CR2, NDR_CR3, NDR_CR4, NDR_CR5, NDR_CR6, NDR_CR7,
NDR_CR8, NDR_CR9, NDR_CR10, NDR_CR11, NDR_CR12, NDR_CR13, NDR_CR14, NDR_CR15,
};

enum
{
REG_DR0, REG_DR1, REG_DR2, REG_DR3, REG_DR4, REG_DR5, REG_DR6, REG_DR7,
REG_DR8, REG_DR9, REG_DR10, REG_DR11, REG_DR12, REG_DR13, REG_DR14, REG_DR15,
NDR_DR0, NDR_DR1, NDR_DR2, NDR_DR3, NDR_DR4, NDR_DR5, NDR_DR6, NDR_DR7,
NDR_DR8, NDR_DR9, NDR_DR10, NDR_DR11, NDR_DR12, NDR_DR13, NDR_DR14, NDR_DR15,
};

enum
{
REG_TR0, REG_TR1, REG_TR2, REG_TR3, REG_TR4, REG_TR5, REG_TR6, REG_TR7,
REG_TR8, REG_TR9, REG_TR10, REG_TR11, REG_TR12, REG_TR13, REG_TR14, REG_TR15,
NDR_TR0, NDR_TR1, NDR_TR2, NDR_TR3, NDR_TR4, NDR_TR5, NDR_TR6, NDR_TR7,
NDR_TR8, NDR_TR9, NDR_TR10, NDR_TR11, NDR_TR12, NDR_TR13, NDR_TR14, NDR_TR15,
};

enum
{
REG_K0, REG_K1, REG_K2, REG_K3, REG_K4, REG_K5, REG_K6, REG_K7,
NDR_K0, NDR_K1, NDR_K2, NDR_K3, NDR_K4, NDR_K5, NDR_K6, NDR_K7,
};

enum
{
REG_BND0, REG_BND1, REG_BND2, REG_BND3,
NDR_BND0, NDR_BND1, NDR_BND2, NDR_BND3,
};

enum
{
REG_ST0, REG_ST1, REG_ST2, REG_ST3, REG_ST4, REG_ST5, REG_ST6, REG_ST7,
NDR_ST0, NDR_ST1, NDR_ST2, NDR_ST3, NDR_ST4, NDR_ST5, NDR_ST6, NDR_ST7,
};

enum
{
REG_XMM0, REG_XMM1, REG_XMM2, REG_XMM3, REG_XMM4, REG_XMM5, REG_XMM6, REG_XMM7,
REG_XMM8, REG_XMM9, REG_XMM10, REG_XMM11, REG_XMM12, REG_XMM13, REG_XMM14, REG_XMM15,
REG_XMM16, REG_XMM17, REG_XMM18, REG_XMM19, REG_XMM20, REG_XMM21, REG_XMM22, REG_XMM23,
REG_XMM24, REG_XMM25, REG_XMM26, REG_XMM27, REG_XMM28, REG_XMM29, REG_XMM30, REG_XMM31,
NDR_XMM0, NDR_XMM1, NDR_XMM2, NDR_XMM3, NDR_XMM4, NDR_XMM5, NDR_XMM6, NDR_XMM7,
NDR_XMM8, NDR_XMM9, NDR_XMM10, NDR_XMM11, NDR_XMM12, NDR_XMM13, NDR_XMM14, NDR_XMM15,
NDR_XMM16, NDR_XMM17, NDR_XMM18, NDR_XMM19, NDR_XMM20, NDR_XMM21, NDR_XMM22, NDR_XMM23,
NDR_XMM24, NDR_XMM25, NDR_XMM26, NDR_XMM27, NDR_XMM28, NDR_XMM29, NDR_XMM30, NDR_XMM31,
};

enum
{
REG_YMM0, REG_YMM1, REG_YMM2, REG_YMM3, REG_YMM4, REG_YMM5, REG_YMM6, REG_YMM7,
REG_YMM8, REG_YMM9, REG_YMM10, REG_YMM11, REG_YMM12, REG_YMM13, REG_YMM14, REG_YMM15,
REG_YMM16, REG_YMM17, REG_YMM18, REG_YMM19, REG_YMM20, REG_YMM21, REG_YMM22, REG_YMM23,
REG_YMM24, REG_YMM25, REG_YMM26, REG_YMM27, REG_YMM28, REG_YMM29, REG_YMM30, REG_YMM31,
NDR_YMM0, NDR_YMM1, NDR_YMM2, NDR_YMM3, NDR_YMM4, NDR_YMM5, NDR_YMM6, NDR_YMM7,
NDR_YMM8, NDR_YMM9, NDR_YMM10, NDR_YMM11, NDR_YMM12, NDR_YMM13, NDR_YMM14, NDR_YMM15,
NDR_YMM16, NDR_YMM17, NDR_YMM18, NDR_YMM19, NDR_YMM20, NDR_YMM21, NDR_YMM22, NDR_YMM23,
NDR_YMM24, NDR_YMM25, NDR_YMM26, NDR_YMM27, NDR_YMM28, NDR_YMM29, NDR_YMM30, NDR_YMM31,
};

enum
{
REG_ZMM0, REG_ZMM1, REG_ZMM2, REG_ZMM3, REG_ZMM4, REG_ZMM5, REG_ZMM6, REG_ZMM7,
REG_ZMM8, REG_ZMM9, REG_ZMM10, REG_ZMM11, REG_ZMM12, REG_ZMM13, REG_ZMM14, REG_ZMM15,
REG_ZMM16, REG_ZMM17, REG_ZMM18, REG_ZMM19, REG_ZMM20, REG_ZMM21, REG_ZMM22, REG_ZMM23,
REG_ZMM24, REG_ZMM25, REG_ZMM26, REG_ZMM27, REG_ZMM28, REG_ZMM29, REG_ZMM30, REG_ZMM31,
NDR_ZMM0, NDR_ZMM1, NDR_ZMM2, NDR_ZMM3, NDR_ZMM4, NDR_ZMM5, NDR_ZMM6, NDR_ZMM7,
NDR_ZMM8, NDR_ZMM9, NDR_ZMM10, NDR_ZMM11, NDR_ZMM12, NDR_ZMM13, NDR_ZMM14, NDR_ZMM15,
NDR_ZMM16, NDR_ZMM17, NDR_ZMM18, NDR_ZMM19, NDR_ZMM20, NDR_ZMM21, NDR_ZMM22, NDR_ZMM23,
NDR_ZMM24, NDR_ZMM25, NDR_ZMM26, NDR_ZMM27, NDR_ZMM28, NDR_ZMM29, NDR_ZMM30, NDR_ZMM31,
};

enum
{
REG_GDTR, REG_IDTR, REG_LDTR, REG_TR,
NDR_GDTR, NDR_IDTR, NDR_LDTR, NDR_TR,
};

enum
{
REG_X87_CONTROL, REG_X87_TAG, REG_X87_STATUS,
NDR_X87_CONTROL, NDR_X87_TAG, NDR_X87_STATUS,
};

enum
{
REG_XCR0, REG_XCR1, REG_XCR_ANY = 0xFF,
NDR_XCR0, NDR_XCR1, NDR_XCR_ANY = 0xFF,
};

#define REG_IA32_TSC 0x00000010
#define REG_IA32_SYSENTER_CS 0x00000174
#define REG_IA32_SYSENTER_ESP 0x00000175
#define REG_IA32_SYSENTER_EIP 0x00000176
#define REG_IA32_STAR 0xC0000081
#define REG_IA32_LSTAR 0xC0000082
#define REG_IA32_FMASK 0xC0000084
#define REG_IA32_FS_BASE 0xC0000100
#define REG_IA32_GS_BASE 0xC0000101
#define REG_IA32_KERNEL_GS_BASE 0xC0000102
#define REG_IA32_TSC_AUX 0xC0000103
#define REG_MSR_ANY 0xFFFFFFFF
#define NDR_IA32_TSC 0x00000010
#define NDR_IA32_SYSENTER_CS 0x00000174
#define NDR_IA32_SYSENTER_ESP 0x00000175
#define NDR_IA32_SYSENTER_EIP 0x00000176
#define NDR_IA32_STAR 0xC0000081
#define NDR_IA32_LSTAR 0xC0000082
#define NDR_IA32_FMASK 0xC0000084
#define NDR_IA32_FS_BASE 0xC0000100
#define NDR_IA32_GS_BASE 0xC0000101
#define NDR_IA32_KERNEL_GS_BASE 0xC0000102
#define NDR_IA32_TSC_AUX 0xC0000103
#define NDR_MSR_ANY 0xFFFFFFFF

#define REG_RFLAG_CF (1 << 0)
#define REG_RFLAG_PF (1 << 2)
#define REG_RFLAG_AF (1 << 4)
#define REG_RFLAG_ZF (1 << 6)
#define REG_RFLAG_SF (1 << 7)
#define REG_RFLAG_TF (1 << 8)
#define REG_RFLAG_IF (1 << 9)
#define REG_RFLAG_DF (1 << 10)
#define REG_RFLAG_OF (1 << 11)
#define REG_RFLAG_IOPL (3 << 12)
#define REG_RFLAG_NT (1 << 14)
#define REG_RFLAG_RF (1 << 16)
#define REG_RFLAG_VM (1 << 17)
#define REG_RFLAG_AC (1 << 18)
#define REG_RFLAG_VIF (1 << 19)
#define REG_RFLAG_VIP (1 << 20)
#define REG_RFLAG_ID (1 << 21)
#define NDR_RFLAG_CF (1 << 0)
#define NDR_RFLAG_PF (1 << 2)
#define NDR_RFLAG_AF (1 << 4)
#define NDR_RFLAG_ZF (1 << 6)
#define NDR_RFLAG_SF (1 << 7)
#define NDR_RFLAG_TF (1 << 8)
#define NDR_RFLAG_IF (1 << 9)
#define NDR_RFLAG_DF (1 << 10)
#define NDR_RFLAG_OF (1 << 11)
#define NDR_RFLAG_IOPL (3 << 12)
#define NDR_RFLAG_NT (1 << 14)
#define NDR_RFLAG_RF (1 << 16)
#define NDR_RFLAG_VM (1 << 17)
#define NDR_RFLAG_AC (1 << 18)
#define NDR_RFLAG_VIF (1 << 19)
#define NDR_RFLAG_VIP (1 << 20)
#define NDR_RFLAG_ID (1 << 21)

#endif
4 changes: 2 additions & 2 deletions inc/version.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@
#define DISASM_VER_H

#define DISASM_VERSION_MAJOR 1
#define DISASM_VERSION_MINOR 26
#define DISASM_VERSION_REVISION 3
#define DISASM_VERSION_MINOR 27
#define DISASM_VERSION_REVISION 0

#endif // DISASM_VER_H
4 changes: 2 additions & 2 deletions isagenerator/generate_tables.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -540,7 +540,7 @@ def cdef_instruction(self):
if m == '1' or m == '0':
dst = dst + self.RevFlagsAccess['u']
for f in dst:
flg += '|REG_RFLAG_%s' % f.upper()
flg += '|NDR_RFLAG_%s' % f.upper()
c += "\n %s," % flg

# Add the instruction operands
Expand Down Expand Up @@ -1202,7 +1202,7 @@ def generate_features(features, fname):
f.write('\n')

for c in features:
f.write('#define ND_CFF_%s%sND_CFF(%s, %s, %s, %s)\n' % (c.Name, ' ' * (25 - len(c.Name)), c.Leaf, c.SubLeaf, 'REG_' + c.Reg, c.Bit))
f.write('#define ND_CFF_%s%sND_CFF(%s, %s, %s, %s)\n' % (c.Name, ' ' * (25 - len(c.Name)), c.Leaf, c.SubLeaf, 'NDR_' + c.Reg, c.Bit))

f.write('\n')

Expand Down
4 changes: 2 additions & 2 deletions pydis/_pydis/pydis.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -33,7 +33,7 @@ nd_vsnprintf_s(char *str, size_t sizeOfBuffer, size_t count, const char *format,
return vsnprintf(str, count, format, args);
}

int nd_memset(void *s, int c, size_t n)
void *nd_memset(void *s, int c, size_t n)
{
memset(s, c, n);
return memset(s, c, n);
}

0 comments on commit 144baa5

Please sign in to comment.