Multiple changes

- Add support for AVX512-FP16 instructions, as per https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html - Bug fix: zeroing with no masking is not supported, so return an error if we encounter such encodings - Bug fix: ignore VEX/EVEX.W field outside 64 bit mode for some instructions - Several other minor fixes and improvements
bitdefender · Jul 8, 2021 · 76d92e7 · 76d92e7
1 parent 5b8b67c
commit 76d92e7
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Showing 86 changed files with 520,640 additions and 151,099 deletions.
diff --git a/bddisasm/bddisasm.c b/bddisasm/bddisasm.c
diff --git a/bddisasm/include/instructions.h b/bddisasm/include/instructions.h
diff --git a/bddisasm/include/mnemonics.h b/bddisasm/include/mnemonics.h
diff --git a/bddisasm/include/nd_crt.h b/bddisasm/include/nd_crt.h
@@ -12,8 +12,7 @@
 #endif
 
 #if defined(_MSC_VER)
-
-typedef char * va_list;
+#include <vadefs.h>
 
 # ifndef _ADDRESSOF
 #  ifdef  __cplusplus
@@ -27,8 +26,6 @@ typedef char * va_list;
 
 #  if defined(AMD64) || defined(WIN64)
 
-extern void __cdecl __va_start(__out va_list *, ...);       // is this exported by VC compiler?
-
 #   define _crt_va_start(ap, x)    ( __va_start(&ap, x) )
 #   define _crt_va_arg(ap, t)      ( ( sizeof(t) > sizeof(QWORD) || ( sizeof(t) & (sizeof(t) - 1) ) != 0 ) \
                                     ? **(t **)( ( ap += sizeof(QWORD) ) - sizeof(QWORD) ) \