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net/mlx5: fix NIC egress flow mismatch in switchdev mode
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[ upstream commit 6d4f106 ]

When E-Switch mode was enabled, the NIC egress flows was implicitly
appended with source vport to match on. If the metadata register C0
was used to maintain the source vport, it was initialized to zero
on packet steering engine entry, the flow could be hit only
if source vport was zero, the register C0 of the packet was not correct
to match in the TX side, this caused egress flow misses.

This patch:
 - removes the implicit source vport match for NIC egress flow.
 - rejects the NIC egress flows on the representor ports at validation.
 - allows the internal NIC egress flows containing the TX_QUEUE items in
   order to not impact hairpins.

Fixes: ce777b1 ("net/mlx5: fix E-Switch flow without port item")

Signed-off-by: Jiawei Wang <jiaweiw@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Acked-by: Ori Kam <orika@nvidia.com>
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jiaweiwsz authored and bluca committed Mar 9, 2022
1 parent c0278ca commit f400875
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Showing 2 changed files with 23 additions and 5 deletions.
2 changes: 2 additions & 0 deletions doc/guides/nics/mlx5.rst
Expand Up @@ -352,6 +352,8 @@ Limitations
from the reference "Clock Queue" completions,
the scheduled send timestamps should not be specified with non-zero MSB.

- The NIC egress flow rules on representor port are not supported.

Statistics
----------

Expand Down
26 changes: 21 additions & 5 deletions drivers/net/mlx5/mlx5_flow_dv.c
Expand Up @@ -5611,8 +5611,10 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
return ret;
last_item = MLX5_FLOW_ITEM_TAG;
break;
case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
last_item = MLX5_FLOW_ITEM_TX_QUEUE;
break;
case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
break;
case RTE_FLOW_ITEM_TYPE_GTP:
ret = flow_dv_validate_item_gtp(dev, items, item_flags,
Expand Down Expand Up @@ -6273,6 +6275,18 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
NULL, "too many header modify"
" actions to support");
}
/*
* Validation the NIC Egress flow on representor, except implicit
* hairpin default egress flow with TX_QUEUE item, other flows not
* work due to metadata regC0 mismatch.
*/
if ((!attr->transfer && attr->egress) && priv->representor &&
!(item_flags & MLX5_FLOW_ITEM_TX_QUEUE))
return rte_flow_error_set(error, EINVAL,
RTE_FLOW_ERROR_TYPE_ITEM,
NULL,
"NIC egress rules on representors"
" is not supported");
return 0;
}

Expand Down Expand Up @@ -10663,12 +10677,14 @@ flow_dv_translate(struct rte_eth_dev *dev,
/*
* When E-Switch mode is enabled, we have two cases where we need to
* set the source port manually.
* The first one, is in case of Nic steering rule, and the second is
* E-Switch rule where no port_id item was found. In both cases
* the source port is set according the current port in use.
* The first one, is in case of NIC ingress steering rule, and the
* second is E-Switch rule where no port_id item was found.
* In both cases the source port is set according the current port
* in use.
*/
if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
(priv->representor || priv->master)) {
(priv->representor || priv->master) &&
!(attr->egress && !attr->transfer)) {
if (flow_dv_translate_item_port_id(dev, match_mask,
match_value, NULL, attr))
return -rte_errno;
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