RISC-V: Relax tail/j to c.j for RV64.

2019-03-30 Andrew Waterman <andrew@sifive.com> bfd/ * elfnn-riscv.c (_bfd_riscv_relax_call): Only check ARCH_SIZE for rd == X_RA case.
bminor · Mar 30, 2019 · ae2b14c · ae2b14c
1 parent 7734102
commit ae2b14c
Show file tree

Hide file tree

Showing 2 changed files with 10 additions and 2 deletions.
diff --git a/bfd/ChangeLog b/bfd/ChangeLog
@@ -1,3 +1,8 @@
+2019-03-30  Andrew Waterman  <andrew@sifive.com>
+
+	* elfnn-riscv.c (_bfd_riscv_relax_call): Only check ARCH_SIZE for
+	rd == X_RA case.
+
 2019-03-29  Max Filippov  <jcmvbkbc@gmail.com>
 
 	* elf32-xtensa.c (shrink_dynamic_reloc_sections): Add

diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c
@@ -3416,9 +3416,12 @@ _bfd_riscv_relax_call (bfd *abfd, asection *sec, asection *sym_sec,
   auipc = bfd_get_32 (abfd, contents + rel->r_offset);
   jalr = bfd_get_32 (abfd, contents + rel->r_offset + 4);
   rd = (jalr >> OP_SH_RD) & OP_MASK_RD;
-  rvc = rvc && VALID_RVC_J_IMM (foff) && ARCH_SIZE == 32;
+  rvc = rvc && VALID_RVC_J_IMM (foff);
 
-  if (rvc && (rd == 0 || rd == X_RA))
+  /* C.J exists on RV32 and RV64, but C.JAL is RV32-only.  */
+  rvc = rvc && (rd == 0 || (rd == X_RA && ARCH_SIZE == 32));
+
+  if (rvc)
     {
       /* Relax to C.J[AL] rd, addr.  */
       r_type = R_RISCV_RVC_JUMP;