My goal is to use the Avnet MiniZed for small prototypes of hardware accelerators running on the FPGA ("processing logic" or PL) that can talk to the Arm core ("processing system" or PS). Keep that purpose in mind if you choose to follow these steps.
The MiniZed is fairly new (as of starting this repository in Oct 2017), so there is still a limited number of targeted tutorials. Fortunately, there are lots of close-enough tutorials for other Zynq boards including older Avnet boards.
Since the Zynq combines hardware and software development and MiniZed is an introductory board, I figure there must be other mere mortals like myself using it. This documentation is written from that perspective. If you have tips, please contribute by issuing a pull request.
If you get stuck at a certain point in these steps or the examples, create a new issue with the Documentation label.
- Get started with the board, Vivado, and SDK
Follow Avnet's MiniZed tutorials 1-3 (or go to http://zedboard.org/ then go to Support | Reference designs and tutorials | MiniZed).
- Get the PS to talk to PL with existing IP
At this point, you now understand how to create an HDF in Vivado using the block editor and use SDK to create and run applications. Next, get some more interesting PL to talk to the PS. Here is an example I adapted where a C application reads and writes BRAM and issues DMA transfers.
- Get the PS to talk to PL with your own IP
At this point, you have worked with an application where the PS talks to the PL, which included an existing AXI peripheral (BRAM). A good next step is to create an application where the software talks to some custom HDL. I adapted this tutorial. Here are my modications.
Note that this example is quite simple in that the IP is combinational logic only (other than AXI interface). I was able to get it to work the first time on the board without verification in simulation.
- Test the PS + PL in behavioral simulation
Vivado includes a Zynq Verification IP (VIP). Basically, it will let verify your whole block design. In your testbenches you will issue PS commands to emulate what your PS would be doing.
First, try out the Vivado example project by following this video tutorial.
Then, you can try the same thing with your own IP. I have an example walkthrough with a resettable saturating counter.
Another option to learn: when you create a new AXI4 peripheral, there as an option to "Verify with AXI VIP". This will create an example testbench for a AXI peripheral. I haven't edited the user logic yet.
For more information on the Zynq VIP's API, see its documentation.
Here's a VGA pmod demo that besides demonstrating use of pmods also demonstrates using only the PL (so no SDK involvement) https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-z7-pmod-vga-demo/start
- TODO, make it work with block design and PS, use Digilent rgb2vga and create a pmod controller ip. Does digilent have IP packager Interface definitions? Or start with source for some PMOD ip, https://github.com/Digilent/vivado-library/tree/master/ip/Pmods
- Under settings | IP | repositories, you can also import interfaces, not just ip. So I imported the contents of Digilent's directory here https://github.com/Digilent/vivado-library/tree/master/if
- Use pinout in https://reference.digilentinc.com/reference/programmable-logic/zybo/reference-manual
- and lazily use the https://github.com/Digilent/Zybo-Z7-10-Pmod-VGA/blob/master/src/constraints/Zybo-Z7-Master.xdc to see which PMOD ports the VGA ports are connected to
- copy the clock configuration from https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-z7-pmod-vga-demo/start
- (just pick requested frequency, and turn off optional outputs reset and locked)
PMOD IPs tutorial https://reference.digilentinc.com/learn/programmable-logic/tutorials/pmod-ips/start
- note that there is no PMOD VGA IP currently, but there is an rgb to VGA IP, so could make a PMOD vga ip to connect it to
Easy connection of IOs, using the board tab. Rely on the IO constraints already provided by the board definition files
- create block design
- click board tab (same window as sources, design,...)
- right click an IO and Connect board component