Implemented MOVDIRI instruction (#129)

Co-authored-by: Stanislav Shwartsman <sshwarts@users.sourceforge.net>
bochs-emu · Nov 11, 2023 · f5b54a4 · f5b54a4
1 parent 620d091
commit f5b54a4
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Showing 7 changed files with 25 additions and 6 deletions.
diff --git a/bochs/CHANGES b/bochs/CHANGES
@@ -7,8 +7,8 @@ Brief summary :
   - Bugfixes for CPU emulation correctness (MONITOR/MWAIT, VMX/SVM, AVX-512, SHA fixes)
   ! Implemented VMX MBE (Mode Based Execution Control) emulation required for Windows 11 guest
   ! Implemented Linear Address Separation (LASS) extension
-  ! Implemented new published Intel instruction sets:
-     - AVX512 BF16, AVX IFMA52, VNNI-INT8, VNNI-INT16, AVX-NE-CONVERT, CMPCCXADD, SM3, SM4, SHA512, WRMSRNS, SERIALIZE
+  ! Implemented recently published Intel instruction sets:
+    - MOVDIRI, AVX512 BF16, AVX IFMA52, VNNI-INT8, VNNI-INT16, AVX-NE-CONVERT, CMPCCXADD, SM3, SM4, SHA512, WRMSRNS, SERIALIZE
   - Improved 64-bit guest support in Bochs internal debugger, added new internal debugger commands
   - Bochs debugger enhanced with new commands (setpmem, loadmem, deref, ...)
     Enhanced magic breakpoint capabilities. Refer to user documentation for more details.

diff --git a/bochs/cpu/cpuid.cc b/bochs/cpu/cpuid.cc
@@ -1026,8 +1026,12 @@ Bit32u bx_cpuid_t::get_std_cpuid_leaf_7_ecx(Bit32u extra) const
   // [24:24] reserved
   // [25:25] CLDEMOTE: CLDEMOTE instruction support - not supported
   // [26:26] reserved
-  // [27:27] MOVDIRI: MOVDIRI instruction support - not supported
-  // [28:28] MOVDIRI64: MOVDIRI64 instruction support - not supported
+
+  // [27:27] MOVDIRI: MOVDIRI instruction support
+  if (is_cpu_extension_supported(BX_ISA_MOVDIRI))
+    ecx |= BX_CPUID_STD7_SUBLEAF0_ECX_MOVDIRI;
+
+  // [28:28] MOVDIR64B: MOVDIR64B instruction support - not supported
   // [29:29] ENQCMD: Enqueue Stores support - not supported
   // [30:30] SGX_LC: SGX Launch Configuration - not supported
 

diff --git a/bochs/cpu/decoder/features.h b/bochs/cpu/decoder/features.h
@@ -134,3 +134,4 @@ x86_feature(BX_ISA_WRMSRNS, "wrmsrns")                                  /* Non-S
 x86_feature(BX_ISA_CMPCCXADD, "cmpccxadd")                              /* CMPccXADD instructions */
 x86_feature(BX_ISA_SERIALIZE, "serialize")                              /* SERIALIZE instruction */
 x86_feature(BX_ISA_LASS, "lass")                                        /* Linear Address Space Separation support */
+x86_feature(BX_ISA_MOVDIRI, "movdiri")                                  /* MOVDIRI instruction support */
diff --git a/bochs/cpu/decoder/fetchdecode32.cc b/bochs/cpu/decoder/fetchdecode32.cc
@@ -891,7 +891,7 @@ static BxOpcodeDecodeDescriptor32 decode32_descriptor[] =
    /* 0F 38 F6 */ { &decoder32_modrm, BxOpcodeTable0F38F6 },
    /* 0F 38 F7 */ { &decoder_ud32, NULL },
    /* 0F 38 F8 */ { &decoder_ud32, NULL },
-   /* 0F 38 F9 */ { &decoder32_modrm, BxOpcodeTable0F38F6 },
+   /* 0F 38 F9 */ { &decoder32_modrm, BxOpcodeTable0F38F9 },
    /* 0F 38 FA */ { &decoder_ud32, NULL },
    /* 0F 38 FB */ { &decoder_ud32, NULL },
    /* 0F 38 FC */ { &decoder_ud32, NULL },

diff --git a/bochs/cpu/decoder/fetchdecode64.cc b/bochs/cpu/decoder/fetchdecode64.cc
@@ -903,7 +903,7 @@ static BxOpcodeDecodeDescriptor64 decode64_descriptor[] =
    /* 0F 38 F6 */ { &decoder64_modrm, BxOpcodeTable0F38F6 },
    /* 0F 38 F7 */ { &decoder_ud64, NULL },
    /* 0F 38 F8 */ { &decoder_ud64, NULL },
-   /* 0F 38 F9 */ { &decoder64_modrm, BxOpcodeTable0F38F6 },
+   /* 0F 38 F9 */ { &decoder64_modrm, BxOpcodeTable0F38F9 },
    /* 0F 38 FA */ { &decoder_ud64, NULL },
    /* 0F 38 FB */ { &decoder_ud64, NULL },
    /* 0F 38 FC */ { &decoder_ud64, NULL },

diff --git a/bochs/cpu/decoder/fetchdecode_opmap_0f38.h b/bochs/cpu/decoder/fetchdecode_opmap_0f38.h
@@ -215,6 +215,14 @@ static const Bit64u BxOpcodeTable0F38F6[] = {
   last_opcode(ATTR_SSE_PREFIX_F3, BX_IA_ADOX_GdEd)
 };
 
+// opcode 0F 38 F9
+static const Bit64u BxOpcodeTable0F38F9[] = {
+#if BX_SUPPORT_X86_64
+  form_opcode(ATTR_OS64 | ATTR_MOD_MEM | ATTR_SSE_NO_PREFIX, BX_IA_MOVDIRI_MqGq),
+#endif
+  last_opcode(            ATTR_MOD_MEM | ATTR_SSE_NO_PREFIX, BX_IA_MOVDIRI_MdGd)
+};
+
 #endif // BX_CPU_LEVEL >= 6
 
 #endif // BX_FETCHDECODE_OPMAP_0F38_H
diff --git a/bochs/cpu/decoder/ia_opcodes.def b/bochs/cpu/decoder/ia_opcodes.def
@@ -2722,6 +2722,12 @@ bx_define_opcode(BX_IA_RDSEED_Ed, "rdseed", "rdseedl", NULL, &BX_CPU_C::RDSEED_E
 bx_define_opcode(BX_IA_RDSEED_Eq, "rdseed", "rdseedq", NULL, &BX_CPU_C::RDSEED_Eq, BX_ISA_RDSEED, OP_Eq, OP_NONE, OP_NONE, OP_NONE, 0)
 #endif
 
+// MOVDIRI
+bx_define_opcode(BX_IA_MOVDIRI_MdGd, "movdiri", "movdiril", &BX_CPU_C::MOV32_EdGdM, NULL, BX_ISA_MOVDIRI, OP_Md, OP_Gd, OP_NONE, OP_NONE, 0)
+#if BX_SUPPORT_X86_64
+bx_define_opcode(BX_IA_MOVDIRI_MqGq, "movdiri", "movdiriq", &BX_CPU_C::MOV_EqGqM, NULL, BX_ISA_MOVDIRI, OP_Mq, OP_Gq, OP_NONE, OP_NONE, 0)
+#endif
+
 #if BX_SUPPORT_AVX
 bx_define_opcode(BX_IA_KADDW_KGwKHwKEw, "kaddw", "kaddw", &BX_CPU_C::BxError, &BX_CPU_C::KADDW_KGwKHwKEwR, BX_ISA_AVX512_DQ, OP_KGw, OP_KHw, OP_KEw, OP_NONE, BX_PREPARE_OPMASK)
 bx_define_opcode(BX_IA_KADDQ_KGqKHqKEq, "kaddq", "kaddq", &BX_CPU_C::BxError, &BX_CPU_C::KADDQ_KGqKHqKEqR, BX_ISA_AVX512_BW, OP_KGq, OP_KHq, OP_KEq, OP_NONE, BX_PREPARE_OPMASK)